MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet

IC MCU 60K FLASH 8MHZ 32-LQFP

MC908GZ60CFJE

Manufacturer Part Number
MC908GZ60CFJE
Description
IC MCU 60K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GZ60CFJE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC908GZ60CFJE
Manufacturer:
Freescale
Quantity:
4 000
Part Number:
MC908GZ60CFJE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908GZ60CFJE
Manufacturer:
NXP USA Inc.
Quantity:
320
MC68HC908GZ60
MC68HC908GZ48
MC68HC908GZ32
Data Sheet
M68HC08
Microcontrollers
MC68HC908GZ60
Rev. 6.0
04/2007
freescale.com

MC908GZ60CFJE Summary of contents

Page 1

MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32 Data Sheet M68HC08 Microcontrollers MC68HC908GZ60 Rev. 6.0 04/2007 freescale.com ...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved. ...

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... Electrical Characteristics — Updated minimum value for low-voltage inhibit, trip rising voltage (VTRIPR). 21.9.2 CGM Component Information — Updated values for feedback bias resistor MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Description Freescale Semiconductor Page Number(s) N/A 119 212 329 ...

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... CGM Operating Conditions 21.9.2 CGM Component Information 21.9.3 CGM Acquisition/Lock Time Information MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Description — Changed TBMCLKSEL to — Changed COPCLK to — Changed COPCLK to CGMXCLK — Changed BUS_CLK to BUS — ...

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... Revision History MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

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... Chapter 18 Timer Interface Module (TIM1 .263 Chapter 19 Timer Interface Module (TIM2 .279 Chapter 20 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Chapter 21 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Chapter 22 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 333 Appendix A MC68HC908GZ48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Appendix B MC68HC908GZ32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 7 ...

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... List of Chapters MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

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... FLASH-1 Control and Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.2.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.2.2 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6.3 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.4 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.6.5 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 1 General Description and and DDA SSA /V ...

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... Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.2.3 Left Justified Signed Data Mode 3.8.2.4 Eight Bit Truncation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SSAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Freescale Semiconductor ...

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... Acquisition/Lock Time Specifications 4.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 4 Clock Generator Module (CGM DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SSA Chapter 5 Configuration Register (CONFIG) 11 ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 6 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Freescale Semiconductor ...

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... Keyboard Interrupt Module (KBI 125 10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.9 Low-Voltage Inhibit Module (LVI 126 10.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes 13 ...

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... Receive Structures 138 12.4.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6.2 Interrupt Vectors 143 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 MSCAN08 Controller (MSCAN08) Freescale Semiconductor ...

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... Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.4.2 Data Direction Register 176 13.5 Port 178 13.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.5.2 Data Direction Register 178 13.5.3 Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 13 Input/Output (I/O) Ports 15 ...

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... ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.7.1 PTE0/TxD (Transmit Data 203 14.7.2 PTE1/RxD (Receive Data 203 14.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.8.1 ESCI Control Register 204 14.8.2 ESCI Control Register 206 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 14 Freescale Semiconductor ...

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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.7.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 15 System Integration Module (SIM) 17 ...

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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.5 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.7 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 16 Chapter 17 Timebase Module (TBM) Freescale Semiconductor ...

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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.6 TIM2 During Break Interrupts 290 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 18 Timer Interface Module (TIM1) Chapter 19 Timer Interface Module (TIM2) 19 ...

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... Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 21.5 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 21.6 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 21.7 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 21.8 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 20 Development Support Chapter 21 Electrical Specifications Freescale Semiconductor ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 A.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 A.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 B.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 B.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 B.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 22 Appendix A MC68HC908GZ48 Appendix B MC68HC908GZ32 21 ...

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... Table of Contents MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

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... Low-power design; fully static with stop and wait modes 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor and Appendix B MC68HC908GZ32. ...

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... Port C is only 2 bits: PTC0–PTC1; shared with MSCAN module – Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1 and TIM2 modules – Port E is only 2 bits: PTE0–PTE1; shared with ESCI module MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

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... MC68HC908GZ32. 1.4 Pin Assignments Figure 1-2, Figure 1-3, and Figure 1-4 and 64-pin QFP respectively. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Appendix A MC68HC908GZ48 illustrate the pin assignments for the 32-pin LQFP, 48-pin LQFP, MCU Block Diagram and 25 ...

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... PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7– PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1/CAN RX (2, 3) PTC0/CAN TX (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...

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... PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor RST IRQ Pin Assignments ...

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... C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev and PTA2/KBD2/AD10 47 PTA1/KBD1/AD9 46 PTA0/KBD0/AD8 45 PTC6 44 PTC5 43 PTG3/AD19 42 PTG2/AD18 41 PTG1/AD17 40 PTG0/AD16 SSAD REFL DDAD REFH 37 PTB7/AD7 PTB6/AD6 36 35 PTB5/AD5 34 PTB4/AD4 PTB3/AD3 Figure 1-5 Freescale Semiconductor ...

Page 29

... V DDAD SSAD are the reference voltage pins for the ADC. V the V /V pin should be externally filtered and connected to the same voltage potential as V DDAD REFH MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor MCU 0.1 μ Figure 1-5 ...

Page 30

... Chapter 3 Analog-to-Digital Converter and Chapter 3 Analog-to-Digital Converter ) TX Chapter 18 Timer Interface Module (TIM2), Chapter 16 Serial Peripheral Interface (SPI) Chapter 5 Configuration Register Chapter 14 Enhanced Serial Communications Interface Ports. /V pin should be connected SSAD REFL (ADC). Ports, (ADC). (ADC). Chapter (TIM1), Module, Chapter (CONFIG). Freescale Semiconductor ...

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... Never connect unused pins directly to V Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method above are appropriate. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 18 Timer Interface Module and Chapter 13 Input/Output (I/O) (ADC) ...

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... General Description MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

Page 33

... LVI status register, LVISR • $FE0D; FLASH-2 test control register, FLTCR2 • $FE0E; FLASH-1 test control register, FLTCR1 • $FF80; FLASH-1 block protect register, FL1BPR MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Figure 2-1, includes: (Figure 2-1) 33 ...

Page 34

... FLASH-2 CONTROL REGISTER (FL2CR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED UNIMPLEMENTED 16 BYTES FOR A-FAMILY PART MONITOR ROM 352 BYTES RESERVED 6 BYTES FLASH-1 CONTROL REGISTER (FL1CR) RESERVED 67 BYTES FLASH-1 VECTORS 52 BYTES Freescale Semiconductor ...

Page 35

... See page 217. Reset: Read: ESCI Arbiter Data $000B Register (SCIADAT) Write: See page 218. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 ...

Page 36

... SCTIE TCIE SCRIE ILIE SCTE TC SCRF IDLE Unimplemented R = Reserved Bit 0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF Unaffected Freescale Semiconductor ...

Page 37

... Register Low (T1CNTL) Write: See page 273. Reset: Read: TIM1 Counter Modulo $0023 Register High (T1MODH) Write: See page 273. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit Unaffected by reset ...

Page 38

... Indeterminate after reset Bit Indeterminate after reset TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit Unimplemented R = Reserved Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit Unaffected Freescale Semiconductor ...

Page 39

... Read: PLL VCO Select Range $003A Register (PMRS) Write: See page 87. Reset: Read: $003B Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit 15 ...

Page 40

... Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 A3 AD2 AD1 AD0 0 MODE1 MODE0 PTAF3 PTF2 PTF1 PTF0 PTG3 PTG2 PTG1 PTG0 DDRF3 DDRF2 DDRF1 DDRF0 DDRG3 DDRG2 DDRG1 DDRG0 KBIP3 KBIP2 KBIP1 KBIP0 ELS2B ELS2A TOV2 CH2MAX Bit Bit Unaffected Freescale Semiconductor ...

Page 41

... Writing a 0 clears SBSW. Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 237. POR: Read: $FE02 Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit CH3F 0 CH3IE MS3A Bit 15 ...

Page 42

... IF6 IF5 IF4 IF3 IF14 IF13 IF12 IF11 IF22 IF21 IF20 IF19 Bit Bit BRKE BRKA LVIOUT Unimplemented R = Reserved Bit IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 IF24 IF23 HVEN MASS ERASE PGM Bit Bit Unaffected Freescale Semiconductor ...

Page 43

... See page 46. Reset: Read: COP Control Register $FFFF (COPCTL) Write: See page 97. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Vector Priority Lowest MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit BPR7 BPR6 BPR5 BPR7 BPR6 BPR5 ...

Page 44

... TIM1 Channel 0 Vector (Low) $FFF8 PLL Vector (High) IF2 $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) Vector Freescale Semiconductor ...

Page 45

... FLASH-1 control register (FL1CR) • $FFCC–$FFFF: these locations are reserved for user-defined interrupt and reset vectors (see Table 2-1 for details) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Random-Access Memory (RAM) NOTE NOTE NOTE 45 ...

Page 46

... Program operation selected 0 = Program operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE HVEN ( Bit 0 MASS ERASE PGM Freescale Semiconductor ...

Page 47

... FLASH-1. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range. Refer to desired locations are protected. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 48

... Wait for a time, t RCV A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE NOTE NOTE (minimum 4 ms). NOTES Freescale Semiconductor ...

Page 49

... Programming of the FLASH-1 memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: • $XX00 to $XX3F • $XX40 to $XX7F • $XX80 to $XXBF • $XXC0 to $XXFF MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor FLASH-1 Memory (FLASH-1) NOTES 49 ...

Page 50

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE Figure 2-6. NOTES maximum defined as the cumulative high voltage HV HV must satisfy this condition: HV ≤ 64) t maximum HV Freescale Semiconductor ...

Page 51

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-6. FLASH-1 Programming Algorithm Flowchart MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 1 SET PGM BIT READ THE FLASH BLOCK 2 PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ...

Page 52

... FLASH-2 block protect register (FL2BPR) FL2BPR physically resides within FLASH-1 memory addressing space • $FE08: FLASH-2 control register (FL2CR) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE NOTE Freescale Semiconductor ...

Page 53

... Program operation selected 0 = Program operation unselected 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE ...

Page 54

... Bit 0 BPR2 BPR1 BPR0 ↓ ↓ Freescale Semiconductor ...

Page 55

... NVS 5. Set the HVEN bit. 6. Wait for a time, t MERASE 7. Clear the ERASE and MASS bits. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Register. If FL2BPR is programmed with any value other than $FF, the NOTE NOTE (minimum 4 ms). FLASH-2 Memory (FLASH-2) ...

Page 56

... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTES NOTES Freescale Semiconductor ...

Page 57

... PROG programming time to the same row before next erase PROG X NVS NVH PGS MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Figure 2-10. NOTES maximum defined as the cumulative high voltage HV HV must satisfy this condition: HV ≤ ...

Page 58

... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a standby mode. Standby mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE Freescale Semiconductor ...

Page 59

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-10. FLASH-2 Programming Algorithm Flowchart MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 1 SET PGM BIT READ THE FLASH BLOCK 2 PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ...

Page 60

... Memory MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...

Page 61

... I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. A read of a port pin in use by the ADC will return a 0. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ). V is converted by ADIN ...

Page 62

... PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7– PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1/CAN RX (2, 3) PTC0/CAN TX (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...

Page 63

... V . DDAD Connect the V DDAD connect the V SSAD The V pin should be routed carefully for maximum noise immunity. DDAD MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor DDRx PTx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ADC ADC CLOCK CLOCK GENERATOR ADIV2– ...

Page 64

... Right justification will place only the two MSBs in the corresponding ADC data register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This mode of operation typically is used when a 10-bit unsigned result is desired. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev ADC cycles ADC frequency Freescale Semiconductor ...

Page 65

... When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit The COCO bit is not used as a conversion complete flag when interrupts are enabled. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Figure 3-3. ...

Page 66

... Connect the V DDAD NOTE carefully and place bypass DDAD ) SSAD as its ground pin. Connect the V SSAD NOTE cleanly to avoid any offset errors. SSAD pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD Freescale Semiconductor ...

Page 67

... ADC status and control register (ADSCR) • ADC data register (ADRH and ADRL) • ADC clock register (ADCLK) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ) REFH as its upper voltage reference pin. By default, connect the V REFH . External filtering is often necessary to ensure a clean V ...

Page 68

... MCU when the ADC is not being used. Recovery from the disabled state requires one conversion cycle to stabilize. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev AIEN ADCO ADCH4 ADCH3 NOTE Table 3-1. NOTE 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Table 3-1. Care should be taken Freescale Semiconductor ...

Page 69

... ADC converter both in production test and for user applications. ADCH4 ADCH3 ↓ ↓ any unused channels are selected, the resulting ADC conversion will be unknown or re- served. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ...

Page 70

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented Unaffected by reset AD6 AD5 AD4 AD3 Unaffected by reset = Unimplemented ADRH 2 1 Bit 0 AD4 AD3 AD2 ADRL ADRH 2 1 Bit 0 0 AD9 AD8 ADRL AD2 AD1 AD0 Freescale Semiconductor ...

Page 71

... Address: $003D Bit 7 Read: 0 Write: Reset: Address: $003E Read: AD9 Write: Reset: Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset ...

Page 72

... Table 3-2. ADC Clock Divide Ratio ADIV1 ADIV0 ADC Clock Rate ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ ADC input clock ÷ 16 (1) ( bus frequency ≅ 1 MHz ADIV[2: Bit 0 0 MODE0 21.10 5.0-Volt ADC Characteristics. Freescale Semiconductor ...

Page 73

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 73 ...

Page 74

... CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF Figure 4-1. CGM Block Diagram CGMXCLK (TO: SIM, TBM, ADC, MSCAN) A CGMOUT CLOCK SELECT ÷ 2 (TO SIM CIRCUIT SIMDIV2 * WHEN CGMOUT = B (FROM SIM) CGMVCLK CGMINT (TO SIM) Freescale Semiconductor ...

Page 75

... The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor VRS , (71.4 kHz) times a linear factor, L, and a power-of-two factor PLL ...

Page 76

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 4.8 Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications Register.) Register.) 4.5.2 PLL 4.3.8 Base Clock Selector for for Freescale Semiconductor ...

Page 77

... The relationship between the VCO frequency, f reference frequency, f RCLK N, the range multiplier, must be an integer. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor , after entering tracking mode before selecting the PLL as the AL Table 4-1. Variable Definitions Definition ...

Page 78

... VCLK L = Round NOM VRS NOM E × NOM ≤ -------------------------- - f – f VRS VCLK VCLK VRS VCLKDES NOTE to a value determined RCLK Chapter 21 Electrical and f . VCLK BUS Table 4- (1) 2 VRS and f . For proper operation, VCLKDES , and f must be as close as possible VRS Freescale Semiconductor . The ...

Page 79

... L is programmed This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Table 4-3. Numeric Example f RCLK ...

Page 80

... OSCENINSTOP (FROM CONFIG) OSC1 Note: Filter network in box can be replaced with a single capacitor, but will degrade stability. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev CGMXCLK CGMXFC OSC2 Figure 4-2. CGM External Connections Figure V V SSA DDA BYP F2 Freescale Semiconductor 4-2. ...

Page 81

... If this bit is set, the oscillator continues running during stop mode. If this bit is not set (default), the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 4-2.) NOTE ...

Page 82

... Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 Register.) High.) Low.) Register.) Bit PLLF PLLIE PLLON LOCK AUTO ACQ Unimplemented Figure 4-3. CGM I/O Register Summary ) and comes XCLK BCS R R VPR1 MUL11 MUL10 MUL9 Reserved Freescale Semiconductor Bit 0 VPR0 MUL8 0 ...

Page 83

... PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit Change in lock condition change in lock condition MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit MUL7 ...

Page 84

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE NOTE Circuit.). VRS 4.3.3 PLL Circuits, Register.) VCO Power-of-Two ( NOTE 4.3.6 Programming the PLL 4.3.8 Base Clock Selector 4.3.8 Base Clock . VPR1:VPR0 cannot be written when the 4.3.6 Programming the Range Multiplier for detailed instructions Freescale Semiconductor PLL, and ...

Page 85

... In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor LOCK ...

Page 86

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev MUL11 4.3.3 PLL Circuits and 4.3.6 Programming the NOTE MUL6 MUL5 MUL4 MUL3 NOTE for detailed instructions on choosing the 2 1 Bit 0 MUL10 MUL9 MUL8 PLL.) A value of $0000 Bit 0 MUL2 MUL1 MUL0 Freescale Semiconductor ...

Page 87

... The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 4.3.3 PLL Circuits and 4.3.6 Programming the ...

Page 88

... To protect the PLLF bit during the break state, write the BCFE bit. With BCFE at 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE 15.7.3 Break Flag Control Register.) Freescale Semiconductor ...

Page 89

... Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Acquisition/Lock Time Specifications PLL.) 4 ...

Page 90

... Time, the external filter network is critical to the Figure 4-9 (A). Refer to CGMXFC Figure 4-9. PLL Filter 8.2 nF 820 pF 4.7 nF 470 pF 3.3 nF 330 pF 2.2 nF 220 pF 1.8 nF 180 pF 1.5 nF 150 pF 1.2 nF 120 100 pF Figure 4-9 (B) can be replaced by a Table 4-5 for recommended filter SSA ( 2.2 nF Freescale Semiconductor ...

Page 91

... FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-2. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Figure 5-1 and 91 ...

Page 92

... MCLK0 MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC See note tio Table 5-1. MCLK Output Select MCLK0 MCLK Frequency 0 MCLK not enabled 1 0 Clock divided Clock divided by 4 for a more detailed description of the NOTE Chapter 17 Timebase Module (TBM Bit Clock for a more Freescale Semiconductor ...

Page 93

... LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See 1 = LVI module power disabled 0 = LVI module power enabled MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor (CGM). This function is used to keep the timebase running while Chapter 17 Timebase Module Module. 6 ...

Page 94

... COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Chapter 11 Low-Voltage Inhibit NOTE NOTE Chapter 6 Computer Operating Properly (COP) (see Chapter 21 DD Module. Freescale Semiconductor ...

Page 95

... COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 6-1. COP Block Diagram ...

Page 96

... The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the SIM counter and the COP counter. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev NOTE . During the break state, TST NOTE Figure 6-1. 6.4 Freescale Semiconductor ...

Page 97

... Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 98

... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev present on the RST pin. TST Freescale Semiconductor ...

Page 99

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 99 ...

Page 100

... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...

Page 101

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 102

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 102 NOTE 2 1 Bit Freescale Semiconductor ...

Page 103

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 103 ...

Page 104

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

Page 105

... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...

Page 106

... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...

Page 107

... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...

Page 108

... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...

Page 109

... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...

Page 110

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 111

... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 111 ...

Page 112

... CLR D Q SYNCHRONIZER CK IMASK MODE Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ INTERRUPT REQUEST HIGH TO MODE SELECT VOLTAGE DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...

Page 113

... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Support. IRQ Pin ...

Page 114

... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 114 IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...

Page 115

... A keyboard interrupt is latched when one or more keyboard pins are asserted. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 115 ...

Page 116

... PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7– PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1/CAN RX (2, 3) PTC0/CAN TX (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...

Page 117

... See page 120. Reset: Read: Keyboard Interrupt Enable $001B Register (INTKBIER) Write: See page 121. Reset: Read: Keyboard Interrupt Polarity $0448 Register (INTKBIPR) Write: See page 121. Reset: MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor V DD CLR MODEK Bit ...

Page 118

... KBIPx bits in the keyboard interrupt polarity register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 118 NOTE Freescale Semiconductor ...

Page 119

... These registers control and monitor operation of the keyboard module: • Keyboard status and control register (INTKBSCR) • Keyboard interrupt enable register (INTKBIER) • Keyboard interrupt polarity register (INTKBIPR) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 9.7.1 Keyboard Status and Control Low-Power Modes Register. 119 ...

Page 120

... This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on edge and level detect 0 = Keyboard interrupt requests on edges only MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 120 KEYF Unimplemented 2 1 Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...

Page 121

... Each of these read/write bits enables the polarity of the keyboard interrupt pin. Reset clears the keyboard interrupt polarity register Keyboard polarity is rising edge and/or high level 0 = Keyboard polarity is falling edge and/or low level MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 122

... Keyboard Interrupt Module (KBI) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 122 Freescale Semiconductor ...

Page 123

... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 5 Chapter 5 Configuration Register 123 ...

Page 124

... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 124 Freescale Semiconductor ...

Page 125

... The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Computer Operating Properly Module (COP) 125 ...

Page 126

... The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 126 Freescale Semiconductor ...

Page 127

... The MSCAN08 module is inactive in stop mode. The STOP instruction does not affect MSCAN08 register states. Because the internal clock is inactive during stop mode, entering stop mode during an MSCAN08 transmission or reception results in invalid data. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Timer Interface Module (TIM1 and TIM2) 127 ...

Page 128

... ADC conversion complete. • Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program counter with the contents of: $FFDC and $FFDD; TBM interrupt. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 128 voltage resets TRIPF Freescale Semiconductor ...

Page 129

... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal unless the OSCENINSTOP bit is set. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor TRIPF NOTE Exiting Stop Mode voltage resets the MCU ...

Page 130

... Low-Power Modes MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 130 Freescale Semiconductor ...

Page 131

... V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...

Page 132

... V DD TRIPF to remain above the V level, enabling LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF , which causes the MCU TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Bit polling ...

Page 133

... Reset clears the LVIOUT bit. V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is ...

Page 134

... If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 134 Freescale Semiconductor ...

Page 135

... Programmable MSCAN08 clock source either CPU bus clock or crystal oscillator output • Programmable link to timer interface module 1 channel 0 for time-stamping and network synchronization • Low-power sleep mode MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 135 ...

Page 136

... PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7– PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1/CAN RX (2, 3) PTC0/CAN TX (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...

Page 137

... Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ) and one output (CAN RX Figure 12-2 ...

Page 138

... The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 138 12.4.2 Receive Structures. 12.12 Programmer’s Model of Message 1), where the MSCAN08 treats its own messages exactly like Figure 12-3). While the Storage. 12.5 Identifier (2) . The user’s receive handler Freescale Semiconductor ...

Page 139

... All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see 12.12 Programmer’s Model of Message contains an 8-bit “local priority” field (PRIO) (see MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor RxBG RxFG RXF Tx0 ...

Page 140

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 140 (CRFLG)) and two bits in the identifier acceptance control register (see Register). These identifier hit flags (IDHIT1 and IDHIT0) Figure 12-4 12.13.7 (1) when TXE is set and 12.13.5 shows how the 32-bit filter bank Freescale Semiconductor ...

Page 141

... CIDMR0 AC7 CIDAR0 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR2 AC7 CIDAR2 ID ACCEPTED (FILTER 1 HIT) Figure 12-5. Dual 16-Bit Maskable Acceptance Filters MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ID20 IDR1 ID15 ID14 IDR2 ID3 ID2 IDR1 IDE ID10 IDR2 ...

Page 142

... CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 12-6. Quadruple 8-Bit Maskable Acceptance Filters MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 142 ID20 IDR1 ID15 ID14 IDR2 ID2 IDR1 IDE ID10 IDR2 ID7 ID6 IDR3 RTR ID3 ID10 IDR3 ID3 Freescale Semiconductor ...

Page 143

... Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in relative interrupt priority are dependent on the chip integration and to be defined. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) Register. 12.4.2 Receive Structures, has occurred. ...

Page 144

... Local Source Mask WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE RERRIF RERRIE TERRIF TERRIE BOFFIF BOFFIE OVRIF OVRIE RXF RXFIE TXE0 TXEIE0 TXE1 TXEIE1 TXE2 TXEIE2 0) serves as a lock to protect the following registers: Global Mask I bit 12.13.1 Table 12-2 Freescale Semiconductor ...

Page 145

... MSCAN08 starts transmitting or goes into sleep mode directly. MCU or MSCAN08 MSCAN08 SLEEPING SLPRQ = 1 SLPAK = 1 Figure 12-7. Sleep Request/Acknowledge Cycle MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor . CPU Mode STOP (1) SLPAK = X SFTRES = X Figure 12-7). The time when the MSCAN08 enters sleep mode ...

Page 146

... To protect the CAN bus system from fatal consequences resulting from violations of the above rule, the MSCAN08 drives the CAN pin into recessive state power-down mode, no registers can be accessed. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 146 NOTE 12.13.1 MSCAN08 Module NOTE NOTE pin stays in TX Freescale Semiconductor ...

Page 147

... CAN bus rates. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 12.13.2 MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the NOTE ...

Page 148

... Section 10.3. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 148 CGMXCLK ÷ 2 ÷ 2 PLL CLKSRC Figure 12-8. Clocking Scheme f MSCANCLK Presc value (1) (see Figure 12-9 Bit rate = No. of time quanta CGMOUT (TO SIM) BCS (2 * BUS FREQUENCY) MSCANCLK PRESCALER (1 ... 64) Freescale Semiconductor ...

Page 149

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor and 12.13.4 MSCAN08 Bus Timing Register NOTE NRZ SIGNAL TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8... 25 TIME QUANTA = 1 BIT TIME SAMPLE POINT (SINGLE OR TRIPLE SAMPLING) . Table 12-3. Time Segment Syntax System expects transitions to occur on the bus during this period ...

Page 150

... RESERVED 5 BYTES $050D $050E ERROR COUNTERS 2 BYTES $050F $0510 IDENTIFIER FILTER 8 BYTES $0517 $0518 RESERVED 40 BYTES $053F $0540 RECEIVE BUFFER $054F $0550 TRANSMIT BUFFER 0 $055F $0560 TRANSMIT BUFFER 1 $056F $0570 TRANSMIT BUFFER 2 $057F Figure 12-10. MSCAN08 Memory Map Freescale Semiconductor ...

Page 151

... Not applicable for receive buffers Figure 12-11. Message Buffer Organization MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Programmer’s Model of Message Storage Register Name IDENTIFIER REGISTER 0 IDENTIFIER REGISTER 1 IDENTIFIER REGISTER 2 ...

Page 152

... ID1 ID0 RTR DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 Freescale Semiconductor ...

Page 153

... In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent Remote frame 0 = Data frame MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit ID10 ...

Page 154

... In case more than one buffer has the same lowest priority, the message buffer with the lower index number wins. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 154 Table 12-5. Data Length Codes Data Length Code DLC2 DLC1 DLC0 PRIO6 PRIO5 PRIO4 PRIO3 Unaffected by reset Table 12-5 Data Byte Count Bit 0 PRIO2 PRIO1 PRIO0 Freescale Semiconductor ...

Page 155

... Write: Read: $0510 CIDAR0 Write: Read: $0511 CIDAR1 Write: Read: $0512 CIDAR2 Write: Read: $0513 CIDAR3 Write: Figure 12-15. MSCAN08 Control Register Structure MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor SYNCH SJW0 BRP5 BRP4 TSEG22 TSEG21 TSEG20 RWRNIF ...

Page 156

... SYNCH TLNKEN Unimplemented 12.8.1 MSCAN08 Sleep Bit 0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 AM3 AM2 AM1 AM0 R = Reserved 2 1 Bit 0 SLPAK SLPRQ SFTRES 12.9 Timer Mode). If the MSCAN08 detects 12.8.1 MSCAN08 Freescale Semiconductor Link). ...

Page 157

... Programmable Wakeup 1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length of at least t . wup 0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 158

... SJW0 clock, which is used to build up the individual bit timing, q Table 12-7. Baud Rate Prescaler BRP3 BRP2 BRP1 12.10 Clock 12-8). 12-8 Bit 0 BRP2 BRP1 BRP0 clock cycles q Synchronization Jump Width 1 T cycle cycle cycle cycle q Prescaler BRP0 Value ( Freescale Semiconductor System). ...

Page 159

... This setting is not valid. Please refer this case PHASE_SEG1 must be at least 2 time quanta. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE TSEG22 TSEG21 TSEG20 TSEG13 (1) Pres value • number of time quanta f MSCANCLK NOTE Table 12-8. Time Segment Values ...

Page 160

... Condition to set the flag: TWRNIF = (96 → TEC) & RERRIF & TERRIF & BOFFIF 3. Condition to set the flag: RERRIF = (127 → REC → 255) & BOFFIF MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 160 RWRNIF TWRNIF RERRIF TERRIF ( not masked, an error interrupt is pending 2 1 Bit 0 BOFFIF OVRIF RXF ( not ( not Freescale Semiconductor ...

Page 161

... The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. 1. Condition to set the flag: TERRIF = (128 → TEC → 255) & BOFFIF MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Programmer’s Model of Control Registers ( not masked, an error interrupt is pending ...

Page 162

... A receive buffer full (successful message reception) event will result in a receive interrupt interrupt will be generated from this event. The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 162 RWRNIE TWRNIE RERRIE TERRIE NOTE 2 1 Bit 0 BOFFIE OVRIE RXFIE Freescale Semiconductor ...

Page 163

... The associated message buffer is full (loaded with a message due for transmission). To ensure data integrity, no registers of the transmit buffers should be written to while the associated TXE flag is cleared. The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 164

... Figure 12-24. Identifier Acceptance Control Register (CIDAC) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 164 ABTRQ2 ABTRQ1 ABTRQ0 Unimplemented NOTE NOTE IDAM2 IDAM1 IDAM0 Unimplemented 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 12.13.7 MSCAN08 Transmitter Flag 2 1 Bit 0 IDHIT2 IDHIT1 IDHIT0 Freescale Semiconductor ...

Page 165

... Figure 12-25. Receiver Error Counter (CRXERR) This read-only register reflects the status of the MSCAN08 receive error counter. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor summarizes the different settings. In “filter closed” mode no messages IDAM1 IDAM0 Identifier Acceptance Mode ...

Page 166

... Unaffected by reset AC6 AC5 AC4 AC3 Unaffected by reset AC6 AC5 AC4 AC3 Unaffected by reset (CIDAR0–CIDAR3 Bit 0 TXERR2 TXERR1 TXERR0 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 2 1 Bit 0 AC2 AC1 AC0 Freescale Semiconductor ...

Page 167

... Ignore corresponding acceptance code register bit Match corresponding acceptance code register and identifier bits. The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in the CMCR0 is set MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE ...

Page 168

... MSCAN08 Controller (MSCAN08) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 168 Freescale Semiconductor ...

Page 169

... Write: See page 178. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 180. Reset: Figure 13-1. I/O Port Register Summary (Sheet MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset ...

Page 170

... Unaffected by reset = Unimplemented Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 PTAF3 PTF2 PTF1 PTF0 PTG3 PTG2 PTG1 PTG0 Freescale Semiconductor ...

Page 171

... DDRB4 5 DDRB5 6 DDRB6 7 DDRB7 0 DDRC0 MSCAN 1 DDRC1 2 DDRC2 C 3 DDRC3 4 DDRC4 5 DDRC5 6 DDRC6 MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit DDRF7 DDRF6 DDRF5 DDRF4 DDRG7 DDRG6 DDRG5 DDRG4 Unimplemented Module Control KBIE0 KBIE1 KBIE2 KBIE3 ADC[15:8] KBIE4 ...

Page 172

... ELS4B:ELS4A ELS5B:ELS5A ADCH[23:16] — Pin PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK — PTD4/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTE0/TxD PTE1/RxD PTE2 — PTE3 PTE4 PTE5 PTF0 PTF1 PTF2 PTF3 — PTF4/T2CH2 PTF5/T2CH3 PTF6/T2CH4 PTF7/T2CH5 PTG0/AD16 PTG1/AD17 PTG2/AD18 PTG3/AD19 — PTG4/AD20 PTG5/AD21 PTG6/AD22 PTG7/AD23 Freescale Semiconductor ...

Page 173

... PTAx/KBDx/ADx pin, while PTA is read as a digital input during the CPU read cycle. Those ports not selected as analog input channels are considered digital I/O ports. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor PTA6 ...

Page 174

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 174 DDRA6 DDRA5 DDRA4 DDRA3 NOTE Table 13-2 summarizes the operation of the port A pins. DDRAx RESET PTAx Figure 13-4. Port A I/O Circuit 2 1 Bit 0 DDRA2 DDRA1 DDRA0 PTAPUEx INTERNAL PULLUP DEVICE PTAx Freescale Semiconductor ...

Page 175

... These writable bits are software programmable to enable pullup devices on an input port bit Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Table 13-2. Port A Pin Functions Accesses to DDRA I/O Pin ...

Page 176

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 176 PTB6 PTB5 PTB4 Unaffected by reset AD6 AD5 AD4 Figure 13-6. Port B Data Register (PTB) NOTE DDRB6 DDRB5 DDRB4 DDRB3 Bit 0 PTB3 PTB2 PTB1 PTB0 AD3 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...

Page 177

... X Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Table 13-3 summarizes the operation of the port B pins. DDRBx RESET PTBx Figure 13-8. Port B I/O Circuit Table 13-3 ...

Page 178

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 178 NOTE PTC6 PTC5 PTC4 Unaffected by reset = Unimplemented Figure 13-9. Port C Data Register (PTC) Chapter 12 MSCAN08 Controller (MSCAN08 DDRC6 DDRC5 DDRC4 DDRC3 Bit 0 PTC3 PTC2 PTC1 PTC0 CAN CAN RX TX –PTC0/CAN pins are MSCAN08 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...

Page 179

... X = Don’t care 2. I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE Table 13-4 summarizes the operation of the port C pins. DDRCx RESET PTCx Figure 13-11 ...

Page 180

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 180 PTCPUE5 PTCPUE4 PTCPUE3 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 18 Timer Interface Module (TIM1 Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS MCLK and Chapter 19 Freescale Semiconductor ...

Page 181

... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 13-15 shows the port D I/O logic. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Chapter 18 Timer Interface Module (TIM1) (TIM2). Table 13-5. ...

Page 182

... Input, V DDRD7–DDRD0 DD (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUEx INTERNAL PULLUP DEVICE PTDx Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 2 1 Bit 0 PTDPUE2 PTDPUE1 PTDPUE0 Freescale Semiconductor (3) (3) ...

Page 183

... The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor ...

Page 184

... E pins. DDREx RESET PTEx Figure 13-19. Port E I/O Circuit Table 13-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE5–DDRE0 DDRE5–DDRE0 2 1 Bit 0 DDRE2 DDRE1 DDRE0 PTEx Accesses to PTE Read Write Pin PTE5–PTE0 PTE5–PTE0 PTE5–PTE0 Freescale Semiconductor (3) ...

Page 185

... Corresponding port F pin configured as input Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from Figure 13-22 shows the port F I/O logic. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor PTF6 PTF5 PTF4 ...

Page 186

... I/O Pin to DDRF Mode Read/Write (2) DDRF7–DDRF0 Output DDRF7–DDRF0 PTG6 PTG5 PTG4 PTG3 Unaffected by reset AD22 AD21 AD20 AD19 PTFx Accesses to PTF Read WritE (3) Pin PTF7–PTF0 PTF7–PTF0 PTF7–PTF0 Bit 0 PTG2 PTG1 PTG0 AD18 AD17 AD16 Freescale Semiconductor ...

Page 187

... When bit DDRGx reading address $0441 reads the PTGx data latch. When bit DDRGx reading address $0441 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor NOTE 6 5 ...

Page 188

... MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 188 DDRGx RESET PTGx Figure 13-25. Port G I/O Circuit Table 13-8. Port G Pin Functions Accesses to DDRG Read/Write (2) DDRG7–DDRG0 DDRG7–DDRG0 PTGx Accesses to PTG Read Write (3) Pin PTG7–PTG0 PTG7–PTG0 PTG7–PTG0 Freescale Semiconductor ...

Page 189

... Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor 189 ...

Page 190

... PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7– PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1/CAN RX (2, 3) PTC0/CAN TX (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...

Page 191

... BIT BIT 0 BIT 1 START BIT 0 BIT 1 BIT MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Table 14-1 shows the full names and the generic names of the Table 14-1. Pin Name Conventions RxD PTE1/RxD 8-BIT DATA FORMAT OR DATA (BIT M IN SCC1 CLEAR) ...

Page 192

... ENSCI RPF PRE- BAUD RATE SCALER GENERATOR DATA SELECTION ÷ 16 CONTROL ESCI DATA RxD REGISTER SCI_TxD TRANSMIT SHIFT REGISTER BUS CLOCK TXINV ACLK BIT IN SCIACTL ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M LINT WAKE ILTY PEN PTY Freescale Semiconductor TxD ...

Page 193

... Write: See page 212. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 212. Reset: Figure 14-4. ESCI I/O Register Summary MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Bit PDS2 PDS1 PDS0 PSSB4 ALOST ...

Page 194

... BAUD ÷ 16 ESCI DATA REGISTER DIVIDER SHIFT REGISTER TXINV M PEN PARITY GENERATION PTY T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 14-5. ESCI Transmitter Figure INTERNAL BUS 11-BIT TRANSMIT TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE LINT Freescale Semiconductor 14-4. SCI_TxD ...

Page 195

... Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Functional Description 195 ...

Page 196

... TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 14.4.3 Receiver Figure 14-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in 14-4. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 196 NOTE 1. Figure Freescale Semiconductor ...

Page 197

... When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit copy of the eighth bit (bit 7). MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor INTERNAL BUS SCR2 ...

Page 198

... START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 14-7. Receiver Data Sampling Table 14-2. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No LSB Table Noise Flag Freescale Semiconductor ...

Page 199

... FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 Freescale Semiconductor Table 14-3. Data Bit Recovery Data Bit Determination ...

Page 200

... STOP DATA SAMPLES Figure 14-8. Slow Data Figure 14-8, the receiver counts 154 RT cycles at the point 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 14-8, the receiver counts 170 RT cycles at the point 170 163 – × 100 = 4.12% ------------------------- - 170 Freescale Semiconductor ...

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