MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 138

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MSCAN08 Controller (MSCAN08)
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to
the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message
being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no
buffer would then be ready for transmission and the bus would be released.
At least three transmit buffers are required to meet the first of the above requirements under all
circumstances. The MSCAN08 has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN08 implements with
the “local priority” concept described in
12.4.2 Receive
Structures.
12.4.2 Receive Structures
The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are
mapped using a "ping pong" arrangement into a single memory area (see
Figure
12-3). While the
background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive
buffer (RxFG) is addressable by the central processor unit (CPU08). This scheme simplifies the handler
software, because only one address area is applicable for the receive process.
Both buffers have a size of 13 bytes to store the CAN control bits, the identifier (standard or extended),
and the data content. For details, see
12.12 Programmer’s Model of Message
Storage.
The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG), signals the status of the
foreground receive buffer. When the buffer contains a correctly received message with matching
identifier, this flag is set. See
12.13.5 MSCAN08 Receiver Flag Register (CRFLG)
On reception, each message is checked to see if it passes the filter (for details see
12.5 Identifier
Acceptance
Filter) and in parallel is written into RxBG. The MSCAN08 copies the content of RxBG into
(1)
(2)
RxFG
, sets the RXF flag, and generates a receive interrupt to the CPU
. The user’s receive handler
has to read the received message from RxFG and to reset the RXF flag to acknowledge the interrupt and
to release the foreground buffer. A new message which can follow immediately after the IFS field of the
CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the
identifier filter function.
When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the
background receive buffer, RxBG. It does NOT overwrite RxFG, generate a receive interrupt or
acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see
12.13.2 MSCAN08 Module Control Register
1), where the MSCAN08 treats its own messages exactly like
all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it
loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become the receiver.
An overrun condition occurs when both the foreground and the background receive message buffers are
filled with correctly received messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message will be discarded and an error
interrupt with overrun indication will be generated if enabled. The MSCAN08 is still able to transmit
messages with both receive message buffers filled, but all incoming messages are discarded.
1. Only if the RXF flag is not set.
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor