MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 187

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PTG7–PTG0 — Port G Data Bits
AD23–AD16 — Analog-to-Digital Input Bits
13.9.2 Data Direction Register G
Data direction register G (DDRG) determines whether each port G pin is an input or an output. Writing a
1 to a DDRG bit enables the output buffer for the corresponding port G pin; a 0 disables the output buffer.
DDRG7–DDRG0 — Data Direction Register G Bits
Figure 13-25
When bit DDRGx is a 1, reading address $0441 reads the PTGx data latch. When bit DDRGx is a 0,
reading address $0441 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits are software-programmable. Data direction of each port G pin is under the control
of the corresponding bit in data direction register G. Reset has no effect on port G data.
AD23–AD16 are pins used for the input channels to the analog-to-digital converter module. The
channel select bits in the ADC status and control register define which port G pin will be used as an
ADC input and overrides any control from the port I/O logic by forcing that pin as the input to the analog
circuitry.
These read/write bits control port G data direction. Reset clears DDRG7–DDRG0], configuring all port
G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
shows the port G I/O logic.
Address:
Care must be taken when reading port G while applying analog voltages to
AD23–AD16 pins. If the appropriate ADC channel is not enabled, excessive
current drain may occur if analog voltages are applied to the PTGx/ADx pin,
while PTG is read as a digital input during the CPU read cycle. Those ports
not selected as analog input channels are considered digital I/O ports.
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
DDRG7
$0445
Bit 7
0
Figure 13-24. Data Direction Register G (DDRG)
DDRG6
6
0
DDRG5
5
0
Table 13-8
NOTE
NOTE
DDRG4
4
0
summarizes the operation of the port G pins.
DDRG3
3
0
DDRG2
2
0
DDRG1
1
0
DDRG0
Bit 0
0
Port G
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