MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 208

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Enhanced Serial Communications Interface (ESCI) Module
R8 — Received Bit 8
T8 — Transmitted Bit 8
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
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When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset clears the T8 bit.
This read/write bit enables ESCI error CPU interrupt requests generated by the receiver overrun bit,
OR. Reset clears ORIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE.
Reset clears PEIE.
1 = ESCI error CPU interrupt requests from OR bit enabled
0 = ESCI error CPU interrupt requests from OR bit disabled
1 = ESCI error CPU interrupt requests from NE bit enabled
0 = ESCI error CPU interrupt requests from NE bit disabled
1 = ESCI error CPU interrupt requests from FE bit enabled
0 = ESCI error CPU interrupt requests from FE bit disabled
1 = ESCI error CPU interrupt requests from PE bit enabled
0 = ESCI error CPU interrupt requests from PE bit disabled
Address:
Reset:
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$0015
Bit 7
R8
U
Figure 14-12. ESCI Control Register 3 (SCC3)
= Unimplemented
T8
6
0
R
5
0
R
R
4
0
= Reserved
ORIE
3
0
NEIE
U = Unaffected
2
0
FEIE
1
0
Freescale Semiconductor
PEIE
Bit 0
0