MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 213

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

LINR — LIN Receiver Bits
SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
SCR2–SCR0 — ESCI Baud Rate Select Bits
Freescale Semiconductor
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
These read/write bits select the baud rate register prescaler divisor as shown in
clears SCP1 and SCP0.
These read/write bits select the ESCI baud rate divisor as shown in
SCR2–SCR0.
Table
LINT
0
0
0
1
1
1
1
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
14-6. Reset clears LINR.
LINR
0
1
1
0
0
1
1
SCP[1:0]
SCR[2:1:0]
0 0
0 1
1 0
1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 14-7. ESCI Baud Rate Prescaling
Table 14-8. ESCI Baud Rate Selection
M
Table 14-6. ESCI LIN Control Bits
X
0
1
0
1
0
1
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
Prescaler Divisor (BPD)
Baud Rate Divisor (BD)
Baud Rate Register
Functionality
13
1
3
4
128
16
32
64
1
2
4
8
Table
14-8. Reset clears
Table
14-7. Reset
I/O Registers
213