MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 274

IC MCU 60K FLASH 8MHZ 32-LQFP

MC908GZ60CFJE

Manufacturer Part Number
MC908GZ60CFJE
Description
IC MCU 60K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GZ60CFJE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Timer Interface Module (TIM1)
18.8.4 TIM1 Channel Status and Control Registers
Each of the TIM1 channel status and control registers does the following:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
274
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM1 counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the TIM1 channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then
writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent
clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM1 CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM1 overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address: $0025
Address: $0028
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
Figure 18-8. TIM1 Channel Status and Control
T1SC0
T1SC1
= Unimplemented
CH0IE
CH1IE
6
0
6
0
Registers (T1SC0:T1SC1)
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
Freescale Semiconductor
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0

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