MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 309

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.3.1.1 Normal Monitor Mode
If V
of the input clock. If PTB4 is high with V
will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes
a bypass of a divide-by-two stage at the oscillator only if V
CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
When monitor mode was entered with V
as long as V
This condition states that as long as V
V
then the COP will be disabled. In the latter situation, after V
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
20.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then all port B pin requirements and conditions,
including the PTB4 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
An external oscillator of 8 MHz is required for a baud rate of 7200, as the internal bus frequency is
automatically set to the external frequency divided by four.
When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ or
RST.
20.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
Table 20-2
Freescale Semiconductor
TST
TST
is applied to RST after the initial reset to get into monitor mode (when V
is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two
summarizes the differences between user mode and monitor mode.
User
Monitor
Modes
TST
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset
vector has been programmed, the traditional method of applying a voltage,
V
TST
is applied to either IRQ or RST.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
, to IRQ must be used to enter monitor mode.
Vector High
$FFFE
$FEFE
Reset
Vector Low
$FFFF
$FEFF
Reset
Table 20-2. Mode Differences
TST
TST
TST
is maintained on the IRQ pin after entering monitor mode, or if
applied to IRQ upon monitor mode entry, the bus frequency
on IRQ, the computer operating properly (COP) is disabled
Vector High
$FFFC
$FEFC
Break
NOTE
Functions
Vector Low
TST
$FEFD
TST
$FFFD
Break
is applied to IRQ. In this event, the
is applied to the RST pin, V
Vector High
$FFFC
$FEFC
SWI
TST
was applied to IRQ),
Vector Low
Monitor Module (MON)
$FEFD
$FFFD
SWI
TST
can be
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