MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 48

IC MCU 60K FLASH 8MHZ 32-LQFP

MC908GZ60CFJE

Manufacturer Part Number
MC908GZ60CFJE
Description
IC MCU 60K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GZ60CFJE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Memory
2.6.3 FLASH-1 Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is done by using the FLASH-1 block protection
register (FL1BPR). FL1BPR determines the range of the FLASH-1 memory which is to be protected. The
range of the protected area starts from a location defined by FL1BPR and ends at the bottom of the
FLASH-1 memory ($FFFF). When the memory is protected, the HVEN bit can not be set in either ERASE
or PROGRAM operations.
When the FLASH-1 block protect register is programmed with all 0’s, the entire memory is protected from
being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for
program and erase.
When bits within FL1BPR are programmed (0), they lock a block of memory address ranges as shown in
Figure
memory can not be erased or programmed.
2.6.4 FLASH-1 Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH-1 memory:
A. Programming and erasing of FLASH locations can not be performed by code being executed from the
48
10. Wait for a time, t
1. Set both the ERASE bit and the MASS bit in the FLASH-1 control register (FL1CR).
2. Read the FLASH-1 block protect register (FL1BPR).
3. Write to any FLASH-1 address within the FLASH-1 array with any data.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE and MASS bits.
8. Wait for a time, t
9. Clear the HVEN bit.
same FLASH array.
2-4. If FL1BPR is programmed with any value other than $FF, the protected block of FLASH
In performing a program or erase operation, the FLASH-1 block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
The vector locations and the FLASH block protect registers are located in
the same page. FL1BPR and FL2BPR are not protected with special
hardware or software. Therefore, if this page is not protected by FL1BPR
and the vector locations are erased by either a page or a mass erase
operation, then both FL1BPR and FL2BPR will also get erased.
Mass erase is disabled whenever any block is protected (FL1BPR does not
equal $FF).
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
RCV
NVS
MERASE
NVHL
, (typically 1 μs) after which the memory can be accessed in normal read mode.
(minimum 10 μs).
(minimum 100 μs).
(minimum 4 ms).
NOTES
NOTE
NOTE
NOTE
Freescale Semiconductor

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