MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 82

IC MCU 60K FLASH 8MHZ 32-LQFP

MC908GZ60CFJE

Manufacturer Part Number
MC908GZ60CFJE
Description
IC MCU 60K FLASH 8MHZ 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GZ60CFJE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Clock Generator Module (CGM)
4.4.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
directly from the crystal oscillator circuit.
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-3
82
Addr.
$0036
$0037
$0038
PLL control register (PCTL)
(See
PLL bandwidth control register (PBWC)
(See
PLL multiplier select register high (PMSH)
(See
PLL multiplier select register low (PMSL)
(See
PLL VCO range select register (PMRS)
(See
PLL Multiplier Select High
is a summary of the CGM registers.
PLL Bandwidth Control
Register Name
4.5.1 PLL Control
4.5.2 PLL Bandwidth Control
4.5.3 PLL Multiplier Select Register
4.5.4 PLL Multiplier Select Register
4.5.5 PLL VCO Range Select
PLL Control Register
Register (PBWC)
Register (PMSH)
See page 83.
See page 85.
See page 86.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
(PCTL)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Register.)
Figure 4-3. CGM I/O Register Summary
PLLIE
AUTO
Bit 7
0
0
0
0
Figure 4-2
Register.)
= Unimplemented
Register.)
LOCK
PLLF
6
0
0
0
0
High.)
Low.)
shows only the logical relation of CGMXCLK to OSC1
PLLON
ACQ
5
1
0
0
0
BCS
R
4
0
0
0
0
0
= Reserved
MUL11
R
3
0
0
0
0
MUL10
R
2
0
0
0
0
Freescale Semiconductor
XCLK
VPR1
MUL9
1
0
0
0
0
) and comes
VPR0
MUL8
Bit 0
R
0
0
0

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