MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 83

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, and the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
Freescale Semiconductor
NOTES:
Addr.
$003A
$003B
$0039
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register
(PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
PLL Multiplier Select Low
PLL VCO Select Range
Register Name
Address:
Reserved Register
Register (PMRS)
Reset:
Register (PMSL)
Read:
Write:
See page 86.
See page 87.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$0036
PLLIE
Bit 7
0
Figure 4-3. CGM I/O Register Summary (Continued)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
= Unimplemented
Figure 4-4. PLL Control Register (PCTL)
PLLF
6
0
MUL7
VRS7
Bit 7
0
0
0
0
PLLON
5
1
= Unimplemented
MUL6
VRS6
6
1
1
0
0
BCS
4
0
MUL5
VRS5
5
0
0
0
0
R
R
3
0
MUL4
VRS4
R
4
0
0
0
0
= Reserved
= Reserved
R
2
0
MUL3
VRS3
R
3
0
0
0
VPR1
1
0
MUL2
VRS2
R
2
0
0
0
VPR0
Bit 0
0
MUL1
VRS1
R
1
0
0
0
CGM Registers
MUL0
VRS0
Bit 0
R
0
0
1
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