MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 92

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Configuration Register (CONFIG)
MCLKSEL — MCLK Source Select Bit
MCLK1 and MCLK0 — MCLK Output Select Bits
MSCANEN— MSCAN08 Enable Bit
TMBCLKSEL— Timebase Clock Select Bit
92
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS pin to be used as a MCLK output clock.
Once configured for MCLK, the PTD data direction register for PTD0 is used to enable and disable the
MCLK output. S e e
Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
pins. See
MSCAN08 operation.
TMBCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See
detailed description of the external clock operation.
1 = Crystal frequency
0 = Bus frequency
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
Note: MSCANEN is only reset via POR (power-on reset).
Chapter 12 MSCAN08 Controller (MSCAN08)
Address:
Reset:
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Read:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
$001E
T a b le 5 -1
Bit 7
0
0
MCLK1
Figure 5-1. Configuration Register 2 (CONFIG2)
0
0
1
1
= Unimplemented
MCLKSEL
fo r M C L K o p tio n s .
6
0
Table 5-1. MCLK Output Select
MCLK1
MCLK0
5
0
0
1
0
1
MCLK0
NOTE
4
0
MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC
See note
Chapter 17 Timebase Module (TBM)
MCLK Frequency
MCLK not enabled
Clock divided by 2
Clock divided by 4
3
for a more detailed description of the
Clock
2
0
1
0
Freescale Semiconductor
Bit 0
1
for a more