MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 154

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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I/O Ports with Key Wake-up
11.4 Key Wake-Up Input Filter
Technical Data
154
The KWU input signals are filtered by a digital filter which is active only
during STOP mode.
The purpose of the filter is to prevent single pulses shorter than a
specified value from waking the part from STOP.
The filter is composed of an internal oscillator and a majority voting logic.
The filter oscillator starts the oscillation by detecting a triggering edge on
an input if the corresponding interrupt enable bit is set.
The majority voting logic takes three samples of an asserted input pin at
each filter oscillator period and if two samples are taken at the triggering
level, the filter recognizes a valid triggering level and sets the
corresponding interrupt flag. In this way the majority voting logic rejects
the short non-triggering state between two incoming triggering pulses.
As the filter is shared with all KWU inputs, the filter considers any pulse
coming from any input pin for which the corresponding interrupt enable
bit is set.
The timing specification is given for a single pulse. The time interval
between the triggering edges of two following pulses should be greater
than the t
this time interval is shorter than t
the two consecutive pulses as a single valid pulse.
The filter is shared by all the KWU pins. Hence any valid triggering level
on any KWU pin is seen by the filter. The timing specification applies to
the input of the filter.
Freescale Semiconductor, Inc.
For More Information On This Product,
KWSP
I/O Ports with Key Wake-up
Go to: www.freescale.com
in order to be considered as a single pulse by the filter. If
KWSP
, the majority voting logic may treat
MC68HC912DT128A — Rev 4.0
MOTOROLA

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