MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 177

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLLCR — PLL Control Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.
RESET:
LOCKIE
Bit 7
0
PLLON
—
6
(1)
Read and write anytime. Exceptions are listed below for each bit.
LOCKIE — PLL LOCK Interrupt Enable
PLLON — Phase Lock Loop On
AUTO — Automatic Bandwidth Control
Forced to 0 when VDDPLL=0.
Cannot be cleared when BCSP = 1 (PLL selected as bus clock). Forced
to 0 when VDDPLL is at VSS level. In limp-home mode, the output of
PLLON is forced to 1, but the PLLON bit reads the latched value.
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running. See
Electrical
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = PLL LOCK interrupt is disabled
1 = PLL LOCK interrupt is enabled
0 = Turns the PLL off.
1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will
0 = Automatic Mode Control is disabled and the PLL is under
1 = Automatic Mode Control is enabled. ACQ bit is read only.
AUTO
5
1
lock automatically.
software control, using ACQ bit.
Specifications.
Go to: www.freescale.com
ACQ
Clock Functions
4
0
3
0
0
Limp-Home and Fast STOP Recovery modes
PSTP
2
0
LHIE
1
0
NOLHM
Bit 0
—
(2)
Clock Functions
Technical Data
$003C
177