MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 215

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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13.5.1.2 Clock Buffer Hysteresis
MC68HC912DT128A — Rev 4.0
MOTOROLA
The input clock buffer uses an Operational Transconductance Amplifier
(labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify
the input signal on the EXTAL pin into a full-swing clock for use by the
clock generation section of the microcontroller. There is an internal R-C
filter (composed of components RFLT2 and CFLT2 in the figure above),
which creates the DC value to which the EXTAL signal is compared. In
this manner, the clock input buffer can track changes in the EXTAL DC
offset voltage due to process variation as well as external factors such
as leakage.
Because the purpose of the clock input buffer is to amplify relatively low-
swing signals into a full-rail output, the gain of the OTA is very high. In
the configuration shown, this means that very small levels of noise can
be coupled onto the input of the clock buffer resulting in noise
amplification.
To remedy this issue, hysteresis was added to the OTA so that the circuit
could still provide the tolerance to leakage and the high gain required
without the noise sensitivity. Approximately 150mV of hysteresis was
added with a maximum hysteresis over process variation of 350mV. As
such, the clock input buffer will not respond to input signals until they
exceed the hysteresis level. At this point, the input signal due to
oscillation will dominate the total input waveform and narrow clock
pulses due to noise will be eliminated.
This circuit will limit the overall performance of the oscillator block only
in cases where the amplitude of oscillation is less than the level of
hysteresis. The minimum amplitude of oscillation is expected to be in
excess of 750mV and the maximum hysteresis is expected to be less
than 350mV, providing a factor of safety in excess of two.
Freescale Semiconductor, Inc.
For More Information On This Product,
lower amplitude for the Pierce. The amplitude will still be sufficient
for robust operation across process, temperature, and voltage
variance.
Go to: www.freescale.com
Oscillator
MC68HC912Dx128P Pierce Oscillator Specification
Technical Data
Oscillator
215

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