MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 236

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse Width Modulator
Technical Data
236
PWDTYx — PWM Channel Duty Registers
PWDTY0
PWDTY1
PWDTY2
PWDTY3
RESET:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
and then write the counter forcing a new period to start with the new
period value.
Period = Channel-Clock-Period × (PWPER + 1)
Period = Channel-Clock-Period × (2 × PWPER)
Read and write anytime.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx+1)/(PWPERx+1)] × 100%
Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)] × 100%
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx−PWDTYx)/PWPERx] × 100%
Duty cycle = [PWDTYx/PWPERx] × 100%
6
6
6
6
6
1
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over
or the channel is disabled. Reading this register returns the most
recent value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be
the state opposite the PPOLx value.
Freescale Semiconductor, Inc.
For More Information On This Product,
5
5
5
5
5
1
Go to: www.freescale.com
Pulse Width Modulator
4
4
4
4
4
1
3
3
3
3
3
1
2
2
2
2
2
1
MC68HC912DT128A — Rev 4.0
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
1
(CENTR = 0)
(CENTR = 1)
(PPOLx = 0)
(PPOLx = 1)
(PPOLx = 1)
(PPOLx = 0)
MOTOROLA
$0050
$0051
$0052
$0053