MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 262

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912DG128AMPVE
Manufacturer:
FREESCALE
Quantity:
2 902
Part Number:
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Manufacturer:
FREESCALE
Quantity:
800
Part Number:
MC912DG128AMPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128AMPVE
Manufacturer:
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Quantity:
800
PAFLG — Pulse Accumulator A Flag Register
Enhanced Capture Timer
Technical Data
262
RESET:
BIT 7
0
0
6
0
0
CLK1, CLK0 — Clock Select Bits
PAOVI — Pulse Accumulator A Overflow Interrupt enable
PAI — Pulse Accumulator Input Interrupt enable
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
CLK1
0
0
1
1
5
0
0
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Enhanced Capture Timer
CLK0
0
1
0
1
4
0
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock
frequency
3
0
0
2
0
0
Clock Source
MC68HC912DT128A — Rev 4.0
PAOVF
1
0
BIT 0
PAIF
0
MOTOROLA
$00A1

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