MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 263

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PACN3, PACN2 — Pulse Accumulators Count Registers
PACN1, PACN0 — Pulse Accumulators Count Registers
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
RESET:
$00A2
$00A3
$00A4
$00A5
BIT 7
BIT 7
BIt 7
Bit 7
BIt 7
Bit 7
0
0
6
6
6
0
6
6
6
0
PAIF — Pulse Accumulator Input edge Flag
Read or write any time.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form
the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1
in PACTL, $A0) the PACN3 and PACN2 registers contents are
respectively the high and low byte of the PACA.
When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in
PAFLG ($A1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read or write any time.
Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation
mode the trailing edge of the gate signal at the PT7 input pin triggers
PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACN3, PACN2 registers will clear all the flags in
this register when TFFCA bit in register TSCR($86) is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
5
5
5
0
5
5
5
0
Go to: www.freescale.com
Enhanced Capture Timer
4
4
4
0
4
4
4
0
3
3
3
0
3
3
3
0
2
2
2
0
2
2
2
0
1
1
1
0
1
1
1
0
Timer Register Descriptions
Enhanced Capture Timer
BIT 0
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
Technical Data
$00A2, $00A3
$00A4, $00A5
PACN1 (hi)
PACN0 (lo)
PACN3 (hi)
PACN2 (lo)
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