MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 273

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
MCCNT — Modulus Down-Counter Count Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
RESET:
$00B6
$00B7
$00B2
$00B3
$00B4
$00B5
BIt 15
BIT 7
BIT 7
Bit 7
BIt 7
BIt 7
Bit 7
Bit 7
1
0
14
6
6
1
6
6
6
6
6
0
PBOVF — Pulse Accumulator B Overflow Flag
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPAR ($A8) are enabled
(see
Read or write any time.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($86) is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pulse
13
5
5
1
5
5
5
5
5
0
Accumulators).
Go to: www.freescale.com
Enhanced Capture Timer
12
4
4
1
4
4
4
4
4
0
11
3
3
1
3
3
3
3
3
0
10
2
2
1
2
2
2
2
2
0
1
9
1
1
1
1
1
1
1
0
Timer Register Descriptions
Enhanced Capture Timer
BIT 0
Bit 8
Bit 0
1
BIT 0
Bit 0
Bit 0
Bit 0
Bit 0
0
Technical Data
$00B2–$00B5
$00B6, $00B7
MCCNTH
MCCNTL
PA3H
PA2H
PA1H
PA0H
273

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