MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 295

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC68HC912DT128A — Rev 4.0
MOTOROLA
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
LSBF — SPI LSB First enable
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
When MODF is set, MSTR always reads zero. SP0CR1 must be
written as part of a mode fault recovery sequence.
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDRS7.
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Hardware interrupt sequence is requested each time the SPIF
0 = SPI internal hardware is initialized and SPI system is in a low-
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
0 = Slave mode
1 = Master mode
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
or MODF status flag is set
power disabled state.
outputs
Go to: www.freescale.com
Multiple Serial Interface
Figure 16-4
and
Figure
Serial Peripheral Interface (SPI)
16-5.
Multiple Serial Interface
Technical Data
295

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