MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 307

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5.6 Arbitration Procedure
17.5.7 Clock Synchronization
MC68HC912DT128A — Rev 4.0
MOTOROLA
IIC is a true multi-master bus that allows more than one master to be
connected on it. If two or more masters try to control the bus at the same
time, a clock synchronization procedure determines the bus clock, for
which the low period is equal to the longest clock low period and the high
is equal to the shortest one among the masters. The relative priority of
the contending masters is determined by a data arbitration procedure, a
bus master loses arbitration if it transmits logic “1” while another master
transmits logic “0”. The losing masters immediately switch over to slave
receive mode and stop driving SDA output. In this case the transition
from master to slave mode does not generate a STOP condition.
Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
Since wire-AND logic is performed on SCL line, a high-to-low transition
on SCL line affects all the devices connected on the bus. The devices
start counting their low period and once a device's clock has gone low,
it holds the SCL line low until the clock high state is reached. However,
the change of low to high in this device clock may not change the state
of the SCL line if another device clock is still within its low period.
Therefore, synchronized clock SCL is held low by the device with the
longest low period. Devices with shorter low periods enter a high wait
state during this time (see
have counted off their low period, the synchronized clock SCL line is
released and pulled high. There is then no difference between the device
clocks and the state of the SCL line and all the devices start counting
their high periods. The first device to complete its high period pulls the
SCL line low again.
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Inter IC Bus
Figure
17-3). When all devices concerned
Technical Data
Inter IC Bus
IIC Protocol
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