MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 315

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912DT128A — Rev 4.0
MOTOROLA
CAUTION:
NOTE:
NOTE:
If, after trying to generate a START signal and neither the IBB nor IBAL
bits are set after several cycles, the IIC should be disabled and re-
enabled with IBEN bit.
IBAL — Arbitration Lost
If, after trying to generate a START signal and neither the IBB nor IBAL
bits are set after several cycles, the IIC should be disabled and re-
enabled with IBEN bit.
SRW — Slave Read/Write
This bit is only valid when the IIC is in slave mode, a complete address
transfer has occurred with an address match and no other transfers have
been initiated.
1. SDA sampled as low when the master drives a high during an
2. SDA sampled as a low when the master drives a high during the
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
The arbitration lost bit (IBAL) is set by hardware when the arbitration
procedure is lost. Arbitration is lost in the following circumstances:
This bit must be cleared by software, by writing a one to it.
When IAAS is set this bit indicates the value of the R/W command bit
of the calling address sent from the master.
Checking this bit, the CPU can select slave transmit/receive mode
according to the command of the master.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Slave receive, master writing to slave
1 = Slave transmit, master reading from slave
address or data transmit cycle.
acknowledge bit of a data receive cycle.
Go to: www.freescale.com
Inter IC Bus
IIC Register Descriptions
Technical Data
Inter IC Bus
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