MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 318

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRIB — Data Direction for Port IB Register
Inter IC Bus
17.7 IIC Programming Examples
17.7.1 Initialization Sequence
Technical Data
318
RESET:
DDRIB7
Bit 7
0
DDRIB6
Read and write anytime
DDRIB[7:2]— Port IB [7:2] Data direction
DDRIB[5:0] — These bits served as memory locations since there are
no corresponding external port pins for MC68HC912DT128A.
Reset will put the IIC Bus Control Register to its default status. Before
the interface can be used to transfer serial data, an initialization
procedure must be carried out, as follows:
6
0
1. Update the Frequency Divider Register (IBFD) and select the
2. Update the IIC Bus Address Register (IBAD) to define its slave
3. Set the IBEN bit of the IIC Bus Control Register (IBCR) to enable
4. Modify the bits of the IIC Bus Control Register (IBCR) to select
Each bit determines the primary direction for each pin configured as
general-purpose I/O.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Associated pin is a high-impedance input.
1 = Associated pin is an output.
required division ratio to obtain SCL frequency from system clock.
address.
the IIC interface system.
Master/Slave mode, Transmit/Receive mode and interrupt enable
or not.
DDRIB5
5
0
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DDRIB4
Inter IC Bus
4
0
DDRIB3
3
0
DDRIB2
2
0
MC68HC912DT128A — Rev 4.0
DDRIB1
1
0
DDRIB0
Bit 0
0
MOTOROLA
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