MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 343

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.10 Clock System
MC68HC912DT128A — Rev 4.0
MOTOROLA
Figure 18-7
circuitry. With this flexible clocking scheme the msCAN12 is able to
handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
The clock source bit (CLKSRC) in the msCAN12 module control register
(CMCR1) (see
whether the msCAN12 is connected to the output of the crystal oscillator
(EXTALi) or to the system clock (SYSCLK).
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met. Additionally, for
high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.
For microcontrollers without the CGM module, CGMCANCLK is driven
from the crystal oscillator (EXTALi).
A programmable prescaler is used to generate out of msCANCLK the
time quanta (Tq) clock. A time quantum is the atomic unit of time handled
by the msCAN12. A bit time is subdivided into three segments
1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section
10.3.
•
Freescale Semiconductor, Inc.
For More Information On This Product,
SYNC_SEG: This segment has a fixed length of one time
quantum. Signal edges are expected to happen within this section.
SYSCLK
EXTALi
shows the structure of the msCAN12 clock generation
Go to: www.freescale.com
msCAN12 Bus Timing Register 0
MSCAN Controller
Figure 18-7. Clocking Scheme
CLKSRC
CGM
CGMCANCLK
msCAN12
Prescaler
(1...64)
CLKSRC
(CBTR0)) defines
Time quanta
MSCAN Controller
clock
Technical Data
Clock System
(1)
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