MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 347

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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18.12.1 Message Buffer Outline
MC68HC912DT128A — Rev 4.0
MOTOROLA
ADDR
1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.
$01xC
$01xA
$01xB
$01x0
$01x1
$01x2
$01x3
$01x4
$01x5
$01x6
$01x7
$01x8
$01x9
(1)
Figure 18-12. Receive/Transmit Message Buffer Extended Identifier
REGISTER
NOTE:
DSR0
DSR1
DSR2
DSR3
DSR4
DSR5
DSR6
DSR7
IDR0
IDR1
IDR2
IDR3
DLR
Figure 18-12
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in
13 byte data structure are undefined out of reset.
The foreground receive buffer can be read anytime but can not be
written. The transmit buffers can be read or written anytime.
Freescale Semiconductor, Inc.
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
For More Information On This Product,
BIT 7
ID28
ID20
ID14
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
ID6
Go to: www.freescale.com
shows the common 13 byte data structure of receive and
MSCAN Controller
ID27
ID19
ID13
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
ID5
6
ID26
ID18
ID12
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB5
ID4
5
SRR (1) IDE (1)
ID25
ID11
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB4
ID3
4
Programmer’s Model of Message Storage
DLC3
ID10
ID24
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
ID2
3
Figure
DLC2
ID23
ID17
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DB2
ID9
ID1
18-13. All bits of the
2
MSCAN Controller
DLC1
ID22
ID16
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
ID8
ID0
Technical Data
1
DLC0
BIT 0
ID15
ID21
RTR
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
ID7
347

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