MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 355

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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18.13.5 msCAN12 Bus Timing Register 1 (CBTR1)
MC68HC912DT128A — Rev 4.0
MOTOROLA
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
CBTR1
$0103
RESET
0
0
0
0
1
.
.
W
R
0
0
0
0
1
.
.
SAMP
Bit 7
0
0
0
1
1
1
.
.
SAMP — Sampling
TSEG22 – TSEG10 — Time Segment
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in
1. In this case PHASE_SEG1 must be at least 2 TimeQuanta.
Transmit point
TSEG22
Sample point
SYNC_SEG
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point.
Freescale Semiconductor, Inc.
6
0
For More Information On This Product,
0 = One sample per bit.
1 = Three samples per bit
0
1
0
1
1
.
.
Table 18-7. Time segment values
16 Tq clock cycles
TSEG21
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
Go to: www.freescale.com
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the CAN bus at
A node in receive mode will sample the bus at this point. If the three
5
0
this point.
samples per bit option is selected then this point marks the position
of the third sample.
MSCAN Controller
Table 18-6. Time segment syntax
.
.
TSEG20
4
0
Table
TSEG22 TSEG21 TSEG20 Time segment 2
(1)
TSEG13
0
0
1
.
.
.
18-7.
3
0
Programmer’s Model of Control Registers
0
0
1
.
.
TSEG12
2
0
0
1
1
.
.
TSEG11
1
0
MSCAN Controller
8 Tq clock cycles
2 Tq clock cycles
1 Tq clock cycle
Technical Data
TSEG10
.
.
Bit 0
0
355

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