MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 371

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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19.4.3 Sample and Hold Stage
19.4.4 Analog-to-Digital Converter Submodule
19.4.5 Clock Prescaler Function
MC68HC912DT128A — Rev 4.0
MOTOROLA
A Sample and Hold (S/H) stage accepts the analog signal from the input
multiplexer and stores it as a capacitor charge on a storage node in the
module. The sample process uses a three stage approach:
This charge redistribution method eliminates the need for external
sample-and-hold circuitry.
The Analog-to-Digital (A/D) Machine uses a successive approximation
A/D architecture to perform analog to digital conversions. The resolution
of the A/D converter is selectable at either 8 or 10 bits. It functions by
comparing the stored analog sample potential with a series of digitally
generated analog potentials (using CDAC & RDAC arrays). By following
a binary search algorithm, the converter quickly locates the
approximating potential that is nearest to the sampled potential. At the
end of the conversion process (10 module clocks for 8-bit, 12 module
clocks for 10-bit), the Successive Approximation Register (SAR)
contains the nearest approximation to the sampled signal, given the
resolution of the A/D converter, and is transferred to the appropriate
results register in the selected format.
To keep the ATD module clock within the specified frequency range
(note: there is a minimum and maximum frequency), a clock prescaler
function is available. This function divides the system PCLK by a
1. The input signal is sampled onto a sample capacitor (for 2 module
2. The sample amplifier quickly charges the storage node with a
3. The input signal is connected directly to the storage node to
Freescale Semiconductor, Inc.
For More Information On This Product,
clocks).
copy of the sample capacitor potential (for 4 module clocks).
complete the sample for high accuracy (for 2, 4, 8 or 16 module
clocks). Longer sample times allow accurate measurement of
higher impedance sources.
Analog-to-Digital Converter
Go to: www.freescale.com
Analog-to-Digital Converter
Functional Description
Technical Data
371

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