MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 374

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Analog-to-Digital Converter
19.6.2 WAIT Mode
19.6.3 Background Debug (ATD FREEZE) Mode
19.6.4 Module Reset
Technical Data
374
If the ASWAI control bit in ATDCTL2 is set, then the ATD responds to
WAIT mode. If the ASWAI control bit is clear, then the ATD ignores the
WAIT signal. The ATD response to the wait mode is to power down the
module. In this mode, the MCU does not have access to the control,
status or result registers.
When debugging an application, it is useful to have the ATD pause when
a breakpoint is encountered. To accommodate this, there are two
FREEZE bits in the ATDCTL3 register used to select one of three
responses:
Control and timing logic is static allowing the register contents and timing
position to be remembered indefinitely. The analog electronics remains
powered up; however, internal leakage may compromise the accuracy
of a frozen conversion depending on the length of the freeze period.
When the BDM signal is negated clock activity resumes.
Access to the ATD register file is possible during the ‘frozen’ period.
The ATD module is reset on two different events.
The single difference between the two events is that the RST bit event
does not reset the ADPU bit to its reset state value - i.e. the module is
not reset into a powered down state and will be returned to an idle state.
1. The ATD module may ignore the freeze request.
2. It may respond to the freeze request by finishing the current
3. It may respond by immediately ‘freezing’.
1. In the case of a system reset.
2. If the RST bit in the ATDTEST register is activated.
Freescale Semiconductor, Inc.
For More Information On This Product,
conversion and ‘freezing’ before starting the next sample period.
Analog-to-Digital Converter
Go to: www.freescale.com
MC68HC912DT128A — Rev 4.0
MOTOROLA

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