MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 381

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ATD0CTL3/ATD1CTL3 — ATD Control Register 3
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
Bit 7
0
0
6
0
0
READ: any time
WRITE: any time
S1C — Conversion Sequence Length (Least Significant Bit)
FIFO — Result Register FIFO Mode
This control bit works with control bit S8C in ATDCTL5 in determining
how many conversion are performed per sequence.
When the S1C bit is set, a sequence length of 1 is defined. However,
if the S8C bit is also set, the S8C bit takes precedence. For sequence
length coding information see the description for S8C bit in ATDCTL5.
In normal operation, the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first
conversion appears in the first result register, the second result in the
second result register, and so on. In FIFO mode the result register
counter is not reset at the beginning or ending of a conversion
sequence; conversion results are placed in consecutive result
registers between sequences. The result register counter wraps
around when it reaches the end of the result register file. The
conversion counter value in ATDSTAT0 can be used to determine
where in the result register file, the next conversion result will be
placed.
The results register counter is initialized to zero on three events: on
reset, the beginning of a normal (non-FIFO) conversion sequence,
and the end of a normal (non-FIFO) conversion sequence. Therefore,
the reset bit in register ATDTEST1 can be toggled to zero the result
register counter; any sequence allowed to complete normally will zero
the result register counter; a new sequence (non-FIFO) initiated with
a write to ATDCTL4/5 followed by a write to ATDCTL3 to set the FIFO
bit will start a FIFO sequence with the result register initialized.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Result registers maps to the conversion sequence
1 = Result registers do not map to the conversion sequence
5
0
0
Analog-to-Digital Converter
Go to: www.freescale.com
4
0
0
S1C
3
0
FIFO
2
0
FRZ1
1
0
Analog-to-Digital Converter
FRZ0
Bit 0
0
Technical Data
ATD Registers
$0063/$01E3
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