MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 435

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912DT128A — Rev 4.0
MOTOROLA
Num
1. All timings are calculated for normal port drives.
2. Crystal input is required to be within 45% to 55% duty.
3. Reduced drive must be off to meet these timings.
4. Unequalled loading of pins will affect relative timing numbers.
5. This characteristic is affected by clock stretch.
6. Without TAG enabled.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
5
7
8
9
Add N × t
Frequency of operation (E-clock frequency)
Cycle timet
Pulse width, E lowPW
Pulse width, E high
Address delay timet
Address valid time to ECLK riset
Multiplexed address hold timet
Address Hold to Data Valid
Data Hold to High Zt
Read data setup time
Read data hold time
Write data delay timet
Write data hold timet
Write data setup time
Read/write delay timet
Read/write valid time to E riset
Read/write hold timet
Low strobe
Low strobe
Low strobe
Address access time
Access time from E rise
DBE delay from ECLK rise
DBE valid timet
DBE hold time from ECLK fall
cyc
where N = 0, 1, 2, or 3, depending on the number of clock stretches.
(6)
(6)
(6)
cyc
V
DD
delay timet
valid time to E riset
hold timet
= 1/f
DBE
Characteristic
= 5.0 Vdc ± 10%, V
Table 21-14. Multiplexed Expansion Bus Timing
o
(5)
AD
= PW
DHZ
DHW
(5)
RWH
(5)
PW
DDW
EL
RWD
= t
t
Freescale Semiconductor, Inc.
t
LSH
ACCA
(5)
DSW
= t
= t
LSD
EH
EH
cyc
= t
t
= t
For More Information On This Product,
ACCE
(5)
= t
= t
cyc
AD
= t
cyc
= t
/4 + delay
− t
cyc
= t
t
cyc
= PW
= t
DBED
cyc
/2 + delay
cyc
MAH
− 20
RWV
cyc
/4 + delay
DBED
/4 + delay
cyc
(1), (2), (3), (4)
/4 + delay
cyc
= PW
AV
/4 + delay
LSV
/4 + delay
/2 + delay
/4 + delay
EH
− t
= t
= t
= PW
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= PW
SS
= PW
Electrical Specifications
cyc
AD
cyc
− t
EH
= 0 Vdc, T
/4 + delay
DDW
/4 + delay
− t
EL
EL
− t
EL
DSR
DSR
− t
− t
− t
AD
RWD
LSD
A
= T
L
to T
H
, unless otherwise noted
Delay
−16
−11
−26
−26
−2
−2
14
14
19
26
20
—
—
—
—
—
—
—
—
—
—
—
—
Symbol
PW
PW
t
t
t
t
t
t
t
t
t
t
t
t
AHDS
t
t
DBED
DBEH
t
t
t
ACCA
ACCE
t
t
DDW
DHW
DSW
RWD
RWV
RWH
t
MAH
DHR
t
t
DHZ
DSR
DBE
LSD
LSV
LSH
cyc
AD
f
AV
o
EH
EL
Electrical Specifications
0.004
0.125
Min
60
60
15
15
38
20
15
10
5
0
5
3
5
9
0
8 MHz
Technical Data
Tables of Data
Max
250
8.0
45
20
45
50
57
26
22
51
10
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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