MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 474

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Revision History
Technical Data
474
Appendix: Information
Development Support
MC68HC912DT128A
MC68HC912DG128
Appendix: Changes
Mask Set Changes
EEPROM Memory
MSCAN Controller
Practical Aspects
Analog-to-Digital
Clock Functions
Appendix: CGM
Specifications
Converter
Electrical
Section
from
on
Page (in Rev 3.0)
128,
Freescale Semiconductor, Inc.
132
159
159
163
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352
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455
For More Information On This Product,
129
Go to: www.freescale.com
FPOPEN bit added to EEMCR register
Paragraph added to the EEPGM description to clarify block
protection
Note added about consideration of crystal selection due to EMC
emissions
Opening paragraphs of PLL description changed for clarification
In the section on clock loss during normal operation, description of
operation in limp home mode has been expanded for clarification
In
corrected
First two bullets of sleep mode description updated
SLPRQ = 1 description updated
Major rewrite of entire section for clarification
Clock for the BDM has been renamed as BDMCLK, to
differentiaite it from another internal signal, BCLK
Units for I
Reference to supply differential voltage values updated.
V
Analog input differential voltage row added
f
Footnote added restricting external oscillator operating frequency
to 8MHz when using a quartz crystal
Table footnote removed from
Additional paragraphs added describing ATD differences from the
non A suffix device
Section 23.3 A Few Hints For The CGM Crystal Oscillator
Application removed. All points are covered in new
section
Extra bullets added
XTAL
REF
Revision History
Figure
removed
differential voltage row removed
12-6, MSCAN clock source selection via CLKSRC bit
OFF
corrected to nA
New Section
Description of change
Table 21-16
MC68HC912DT128A — Rev 4.0
regarding V
Oscillator
DDPLL
MOTOROLA

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