MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 54

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADDR[15:8]
MODB/IPIP
MODA/IPIP
Pinout and Signal Descriptions
3.4.15 Clock generation module test (CGMTST)
3.4.16 TEST
Technical Data
54
DATA[15:8]
ADDR[7:0]
LSTRB/TA
Pin Name
DATA[7:0]
CGMTST
RESET
EXTAL
ECLK
ECLK
XTAL
GLO
DBE
CAL
R/W
E1,
E0
PE6, PE5
Shared
PB[7:0]
PA[7:0]
port
PE7
PE7
PE7
PE6
PE4
PE3
PE2
-
-
-
Table 3-2. MC68HC912DT128A Signal Description Summary
Number
112-pin
31–24
64–57
37, 38
Pin
47
48
46
36
36
36
37
39
53
54
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested.
This pin is used for factory test purposes. It is recommended that this
pin is not connected in the application, but it may be bonded to 5.5 V max
without issue. Never apply voltage higher than 5.5 V to this pin
Freescale Semiconductor, Inc.
For More Information On This Product,
Crystal driver and external clock input pins. On reset all the device clocks are
An active low bidirectional control signal, RESET acts as an input to initialize the
External bus pins share function with general-purpose I/O ports A and B. In
Data bus control and, in expanded mode, enables the drive control of external
Inverted E clock used to latch the address.
CAL is the output of the Slow Mode programmable clock divider, SLWCLK, and
Clock generation module test output.
State of mode select pins during reset determine the initial operating mode of
E Clock is the output connection for the external bus clock. ECLK is used as a
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O.
Indicates direction of data on expansion bus. Shares function with general-
derived from the EXTAL input frequency. XTAL is the crystal output.
MCU to a known start-up state, and an output when COP or clock monitor
causes a reset.
single chip modes, the pins can be used for I/O. In expanded modes, the pins
are used for the external buses.
buses during external reads.
is used as a calibration reference for functions such as time of day. It is
overridden when DBE function is enabled. It always has a 50% duty.
the MCU. After reset, MODB and MODA can be configured as instruction
queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
timing reference and for address demultiplexing.
The low strobe function is the exclusive-NOR of A0 and the internal SZ8
signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin function
TAGLO used in instruction tagging. See
purpose I/O. Read/write in expanded modes.
Pinout and Signal Descriptions
Go to: www.freescale.com
Description
Development
MC68HC912DT128A — Rev 4.0
Support.
MOTOROLA

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