MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 58

IC MCU 128K FLASH 8MHZ 112-LQFP

MC912DG128AMPVE

Manufacturer Part Number
MC912DG128AMPVE
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128AMPVE

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Pinout and Signal Descriptions
3.5.4 Port H
Technical Data
58
general-purpose I/O. PEAR settings override DDRE settings. Because
PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in
the DDRE register makes the corresponding bit in port E an output;
clearing a bit in the DDRE register makes the corresponding bit in port E
an input. The default reset state of DDRE is all zeroes.
When the PUPE bit in the PUCR register is set, PE[7,3,2,1,0] are pulled
up. PE[7,3,2,0] are active pull-up devices. PUPCR is not in the address
map in peripheral mode.
Neither port E nor DDRE is in the map in peripheral mode or in the
internal map in expanded modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
Port H pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with
either a rising or falling edge signal (KWPH). An interrupt is generated if
the corresponding bit is enabled (KWIEH). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to
Register DDRH determines whether each port H pin is an input or output.
Setting a bit in DDRH makes the corresponding bit in port H an output;
clearing a bit in DDRH makes the corresponding bit in port H an input.
The default reset state of DDRH is all zeroes.
Register KWPH not only determines what type of edge the key wake ups
are triggered, but it also determines what type of resistive load is used
for port H input pins when PUPH bit is set in the PUCR register. Setting
a bit in KWPH makes the corresponding key wake up input pin trigger at
rising edges and loads a pull down in the corresponding port H input pin.
Clearing a bit in KWPH makes the corresponding key wake up input pin
trigger at falling edges and loads a pull up in the corresponding port H
input pin. The default state of KWPH is all zeroes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
I/O Ports with Key
Wake-up.
MC68HC912DT128A — Rev 4.0
Bus Control and
MOTOROLA

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