MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
1 045
Part Number:
MC68LK332ACAG16
Manufacturer:
Freescale Semiconductor
Quantity:
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© MOTOROLA INC., 1993, 1996
Technical Summary
32-Bit Modular Microcontroller
1 Introduction
This document contains information on a new product. Specifications and information herein are subject to change without notice.
The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipula-
tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that
interface through a common intermodule bus (IMB). Standardization facilitates rapid development of
devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a time processor unit
(TPU), a queued serial module (QSM), and a 2-Kbyte static RAM module with TPU emulation capability
(TPURAM).
The MCU can either synthesize an internal clock signal from an external reference or use an external
clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum sys-
tem clock speed is 20.97 MHz. System hardware and software allow changes in clock rate during op-
eration. Because MCU operation is fully static, register and memory contents are not affected by clock
rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this
capability.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
by MC68332TS/D Rev. 2
Order this document
MC68332

MC68LK332ACAG16 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Technical Summary 32-Bit Modular Microcontroller 1 Introduction The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipula- tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications ...

Page 2

... Freescale Semiconductor, Inc. Package Type TPU Type 132-Pin PQFP Motion Control Standard Std w/enhanced PPWA MOTOROLA For More Information On This Product, 2 Table 1 Ordering Information Temperature Frequency Package (MHz) Order Quantity – MHz 2 pc tray 36 pc tray 20 MHz 2 pc tray 36 pc tray – ...

Page 3

... Freescale Semiconductor, Inc. Table 1 Ordering Information (Continued) Package Type TPU Type 144-Pin QFP Motion Control Standard Std w/enhanced PPWA MC68332 For More Information On This Product, MC68332TS/D Temperature Frequency Package (MHz) Order Quantity – MHz 2 pc tray 44 pc tray 20 MHz 2 pc tray 44 pc tray – ...

Page 4

... Freescale Semiconductor, Inc. Section 1 Introduction 1.1 Features ......................................................................................................................................5 1.2 Block Diagram .............................................................................................................................6 1.3 Pin Assignments ..........................................................................................................................7 1.4 Address Map ...............................................................................................................................9 1.5 Intermodule Bus ..........................................................................................................................9 2 Signal Descriptions 2.1 Pin Characteristics ....................................................................................................................10 2.2 MCU Power Connections ..........................................................................................................11 2.3 MCU Driver Types .....................................................................................................................11 2.4 Signal Characteristics ................................................................................................................12 2.5 Signal Function ..........................................................................................................................13 3 System Integration Module 3 ...

Page 5

... Freescale Semiconductor, Inc. 1.1 Features • Central Processing Unit (CPU32) — 32-Bit Architecture — Virtual Memory Implementation — Table Lookup and Interpolate Instruction — Improved Exception Handling for Controller Applications — High-Level Language Support — Background Debugging Mode — Fully Static Operation • ...

Page 6

... Freescale Semiconductor, Inc. 1.2 Block Diagram TPUCH[15:0] TPUCH[15:0] T2CLK T2CLK RXD PQS7/TXD TXD PQS6/PCS3 PCS3 QS5/PCS2 PCS2 PQS4/PCS1 PCS1 PQS3/PCS0/SS PCS0/SS PQS2/SCK SCK PQS1/MOSI MOSI PQS0/MISO MISO BKPT/DSCLK IFETCH/DSI IPIPE/DSO MOTOROLA For More Information On This Product STBY CHIP SELECTS 2 KBYTES TPU ...

Page 7

... Freescale Semiconductor, Inc. 1.3 Pin Assignments STBY 19 ADDR1 20 ADDR2 21 ADDR3 22 ADDR4 23 ADDR5 24 ADDR6 25 ADDR7 26 ADDR8 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 ADDR13 35 ADDR14 36 ADDR15 37 ADDR16 ADDR17 41 ADDR18 42 PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 2 MC68332 132-Pin QFP Pin Assignments MC68332 For More Information On This Product, ...

Page 8

... Freescale Semiconductor, Inc FC0/CS3 4 FC1/CS4 5 FC2/CS5 ADDR19/CS6 6 7 ADDR20/CS7 ADDR21/CS8 8 9 ADDR22/CS9 10 ADDR23/CS10 T2CLK 14 TPUCH15 TPUCH14 15 16 TPUCH13 TPUCH12 TPUCH11 22 TPUCH10 23 TPUCH9 TPUCH8 24 V DDE 25 V SSE 26 27 TPUCH7 28 TPUCH6 29 TPUCH5 30 TPUCH4 31 TPUCH3 32 TPUCH2 33 TPUCH1 34 TPUCH0 Figure 3 MC68332 144-Pin QFP Pin Assignments ...

Page 9

... Freescale Semiconductor, Inc. 1.4 Address Map The following figure is a map of the MCU internal addresses. The RAM array is positioned by the base address registers in the associated RAM control block. Unimplemented blocks are mapped externally. $YFF000 $YFFA00 $YFFA80 RESERVED $YFFB00 TPURAM CONTROL $YFFB40 ...

Page 10

... Freescale Semiconductor, Inc. 2 Signal Descriptions 2.1 Pin Characteristics The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. Refer to the table, MCU Driver Types, for a description of output drivers. An entry in the dis- crete I/O column of the MCU Pin Characteristics table indicates that a pin has an alternate I/O function ...

Page 11

... Freescale Semiconductor, Inc. Table 2 MCU Pin Characteristic (Continued) Pin Mnemonic T2CLK TPUCH[15:0] TSC TXD 2 XFC 2 XTAL NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2. EXTAL, XFC, and XTAL are clock reference connections. 2.2 MCU Power Connections ...

Page 12

... Freescale Semiconductor, Inc. 2.4 Signal Characteristics Table 5 MCU Signal Characteristics Signal Name ADDR[23:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT ...

Page 13

... Freescale Semiconductor, Inc. Table 5 MCU Signal Characteristics (Continued) Signal Name TSC TXD XFC XTAL 2.5 Signal Function Signal Name Mnemonic Address Bus ADDR[23:0] Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request System Clockout CLKOUT Chip Selects ...

Page 14

... Freescale Semiconductor, Inc. Table 6 MCU Signal Function (Continued) Signal Name Mnemonic Quotient Out Reset Read-Modify-Write Cycle Read/Write SCI Receive Data QSPI Serial Clock Size Slave Select TCR2 Clock TPU Channel Pins TPUCH[15:0] Three-State Control SCI Transmit Data External Filter Capacitor MOTOROLA ...

Page 15

... Freescale Semiconductor, Inc. 3 System Integration Module The MCU system integration module (SIM) consists of five functional blocks that control system start- up, initialization, configuration, and external bus. SYSTEM CONFIGURATION AND PROTECTION CLOCK SYNTHESIZER CHIP SELECTS EXTERNAL BUS INTERFACE FACTORY TEST 3.1 Overview The system configuration and protection block controls MCU configuration and operating mode. The block also provides bus and software watchdog monitors ...

Page 16

... Freescale Semiconductor, Inc. Access Address 15 S $YFFA00 S $YFFA02 S $YFFA04 S $YFFA06 S $YFFA08 S $YFFA0A S $YFFA0C S $YFFA0E S/U $YFFA10 S/U $YFFA12 S/U $YFFA14 S $YFFA16 S/U $YFFA18 S/U $YFFA1A S/U $YFFA1C S $YFFA1E S $YFFA20 S $YFFA22 S $YFFA24 S $YFFA26 S $YFFA28 S $YFFA2A S $YFFA2C S $YFFA2E S $YFFA30 S $YFFA32 S $YFFA34 S $YFFA36 S $YFFA38 ...

Page 17

... Freescale Semiconductor, Inc. Table 7 SIM Address Map (Continued) Access Address 15 S $YFFA56 S $YFFA58 S $YFFA5A S $YFFA5C S $YFFA5E S $YFFA60 S $YFFA62 S $YFFA64 S $YFFA66 S $YFFA68 S $YFFA6A S $YFFA6C S $YFFA6E S $YFFA70 S $YFFA72 S $YFFA74 S $YFFA76 $YFFA78 $YFFA7A $YFFA7C $YFFA7E Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. ...

Page 18

... Freescale Semiconductor, Inc. CLOCK 9 2 PRESCALER Figure 6 System Configuration and Protection Block 3.2.1 System Configuration The SIM controls MCU configuration during normal operation and during internal testing. SIMCR —SIM Configuration Register EXOFF FRZSW FRZBM 0 SLVEN RESET DATA11 The SIM configuration register controls system configuration. It can be read or written at any time, ex- cept for the module mapping (MM) bit, which can be written only once ...

Page 19

... Freescale Semiconductor, Inc. EXOFF — External Clock Off 0 = The CLKOUT pin is driven from an internal clock source The CLKOUT pin is placed in a high-impedance state. FRZSW — Freeze Software Enable 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con- tinue to run. ...

Page 20

... Freescale Semiconductor, Inc. 3.2.2 System Protection Control Register The system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written only once following power-on or reset, but can be read at any time. SYPCR —System Protection Control Register ...

Page 21

... Freescale Semiconductor, Inc. 3.2.3 Bus Monitor The internal bus monitor checks for excessively long DSACK response times during normal bus cycles and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The monitor asserts BERR if response time is excessive. DSACK and AVEC response times are measured in clock cycles. The maximum allowable response time can be selected by setting the BMT field ...

Page 22

... Freescale Semiconductor, Inc. 3.2.7 Periodic Interrupt Timer The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing for the PIT is provided by a programmable prescaler driven by the system clock. PICR — Periodic Interrupt Control Register RESET This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be read or written at any time. Bits [15:11] are unimplemented and always return zero. PIRQL[2:0] — ...

Page 23

... Freescale Semiconductor, Inc. 3.3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because MCU operation is fully static, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in the clock rate during operation. ...

Page 24

... Freescale Semiconductor, Inc. When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is critical, especially at near maximum operating frequencies. The relationship between clock signal duty cycle and clock signal period is expressed: 50% — percentage variation of external clock input duty cycle 3 ...

Page 25

... Freescale Semiconductor, Inc. 3.3.3 Clock Control The clock control circuits determine system clock frequency and clock operation under special circum- stances, such as following loss of synthesizer reference or during low-power operation. Clock source is determined by the logic state of the MODCLK pin during reset. SYNCR —Clock Synthesizer Control Register ...

Page 26

... Freescale Semiconductor, Inc. 3.4 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external de- vices. The external bus has 24 address lines and 16 data lines. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word transfers ...

Page 27

... Freescale Semiconductor, Inc. Table 9 CPU32 Address Space Encoding FC2 3.4.3 Address Bus Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted ...

Page 28

... Freescale Semiconductor, Inc. 3.4.8 Data Transfer Mechanism The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (DSACK1 and DSACK0). 3.4.9 Dynamic Bus Sizing The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports ...

Page 29

... Freescale Semiconductor, Inc. ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in- dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base. 3.4.11 Misaligned Operands CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary ...

Page 30

... Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con- trol must have the same number of wait states ...

Page 31

... Freescale Semiconductor, Inc. 3.5.1 Chip-Select Registers Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These regis- ters also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC) latches discrete output data. Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR) ...

Page 32

... Freescale Semiconductor, Inc. CSPAR1 —Chip Select Pin Assignment Register RESET CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect. Table 14 CSPAR1 Pin Assignments CSPAR0 Field Chip Select Signal ...

Page 33

... Freescale Semiconductor, Inc. 3.5.3 Base Address Registers A base address is the starting address for the block enabled by a given chip select. Block size deter- mines the extent of the block above the base address. Each chip select has an associated base register so that an efficient address map can be constructed for each application chip-select base address register is programmed with the same address as a microcontroller module or memory array, an access to that address goes to the module or array and the chip-select signal is not asserted ...

Page 34

... Freescale Semiconductor, Inc. CSORBT —Chip-Select Option Register Boot ROM MODE BYTE R/W RESET CSOR[10:0] —Chip-Select Option Registers MODE BYTE R/W RESET CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera- tions from peripheral memory devices. The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers. ...

Page 35

... Freescale Semiconductor, Inc. DSACK — Data and Size Acknowledge This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. The following table shows the DSACK field encoding. The fast termination encoding (1110) is used for two-cycle access to external memory. SPACE — ...

Page 36

... Freescale Semiconductor, Inc. AVEC — Autovector Enable 0 = External interrupt vector enabled 1 = Autovector enabled This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge cycle not usually used in conjunction with a chip-select pin. If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE = 00) and the AVEC field is set to one, the chip select automatically generates an AVEC in response to the interrupt cycle ...

Page 37

... Freescale Semiconductor, Inc. PEPAR — Port E Pin Assignment Register 15 NOT USED RESET: The bits in this register control the function of each port E pin. Any bit set to one configures the corre- sponding pin as a bus control signal, with the function shown in the following table. Any bit cleared to zero defines the corresponding pin I/O pin, controlled by PORTE and DDRE ...

Page 38

... Freescale Semiconductor, Inc. PFPAR — Port F Pin Assignment Register 15 NOT USED RESET: The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corre- sponding pin I/O pin. Any bit set to one defines the corresponding pin interrupt request signal or MODCLK ...

Page 39

... Freescale Semiconductor, Inc. DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT 3.7.2 Functions of Pins for Other Modules During Reset Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers ...

Page 40

... Freescale Semiconductor, Inc. 3.7.3 Reset Timing The RESET input must be asserted for a specified minimum period in order for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states ...

Page 41

... Freescale Semiconductor, Inc. When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and re- started before normal operation can resume. 3.8 Interrupts Interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service. The CPU32 provides for eight levels of interrupt priority (0– ...

Page 42

... Freescale Semiconductor, Inc. mask lower-priority interrupts during exception processing, and it is decoded by modules that have re- quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. Modules that have requested interrupt service decode the IP value placed on the address bus at the beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond to the cycle ...

Page 43

... Freescale Semiconductor, Inc. 1. The dominant interrupt source supplies a vector number and DSACK signals appropriate to the access. The CPU32 acquires the vector number. 2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the CPU32 generates an autovector number corresponding to interrupt priority ...

Page 44

... Freescale Semiconductor, Inc. 4 Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system perfor- mance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calcu- lation-intensive algorithms and supporting high-level languages ...

Page 45

... Freescale Semiconductor, Inc Figure 10 User Programming Model Figure 11 Supervisor Programming Model Supplement MC68332 For More Information On This Product, MC68332TS (USP CCR 0 A7' (SSP (CCR VBR 2 0 SFC DFC Go to: www.freescale.com Data Registers Address Registers User Stack Pointer Program Counter Condition Code Register ...

Page 46

... Freescale Semiconductor, Inc. 4.3 Status Register The status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte containing the condition codes is the only portion of the register available at the user privilege level referenced as the con- dition code register (CCR) in user programs ...

Page 47

... Freescale Semiconductor, Inc. 4.6 Instruction Set Summary Table 20 Instruction Set Summary Instruction Syntax ABCD Dn, Dn (An), (An) ADD Dn, <ea> <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ # <data>, <ea> ADDX Dn, Dn (An), (An) AND <ea>, Dn Dn, <ea> ANDI # <data>, <ea> ANDI to CCR # <data>, CCR ...

Page 48

... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary(Continued) Instruction Syntax DBcc Dn, label DIVS/DIVU <ea>, Dn DIVSL/DIVUL <ea> <ea>, Dq <ea> EOR Dn, <ea> EORI # <data>, <ea> EORI to CCR # <data>, CCR 1 EORI <data>, SR EXG Rn, Rn EXT Dn Dn EXTB Dn ILLEGAL none JMP Í JSR Í LEA <ea>, An ...

Page 49

... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary(Continued) Instruction Syntax 1 MOVES Rn, <ea> <ea>, Rn MULS/MULU <ea>, Dn <ea>, Dl <ea> NBCD Í NEG Í NEGX Í NOP none NOT Í OR <ea>, Dn Dn, <ea> ORI #<data>, <ea> ORI to CCR #<data>, CCR 1 ORI to SR #<data>, SR PEA Í ...

Page 50

... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary(Continued) Instruction Syntax SWAP Dn TAS Í TBLS/TBLU <ea>, Dn Dym : Dyn, Dn TBLSN/TBLUN <ea>, Dn Dym : Dyn, Dn TRAP #<data> TRAPcc none #<data> TRAPV none TST Í UNLK An 1. Privileged instruction. MOTOROLA For More Information On This Product, 50 Operand Size ...

Page 51

... Freescale Semiconductor, Inc. 4.7 Background Debugging Mode The background debugger on the CPU32 is implemented in CPU microcode. The background debug- ging commands are summarized below. Table 21 Background Debuggung Mode Command Mnemonic Read D/A Register RDREG/RAREG Write D/A Register WDREG/WAREG The data operand is written to the specified address or data ...

Page 52

... Freescale Semiconductor, Inc. 5 Time Processor Unit The time processor unit (TPU) provides optimum performance in controlling time-related activity. The TPU contains a dedicated execution unit, a tri-level prioritized scheduler, data storage RAM, dual-time bases, and microcode ROM. The TPU controls 16 independent, orthogonal channels, each with an as- sociated I/O pin, and is capable of performing any microcoded time function ...

Page 53

... Freescale Semiconductor, Inc. 5.1.2 Input Capture/Input Transition Counter (ITC) Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition or specified number of transitions, and then generate an interrupt request to notify the CPU. A channel can perform input captures continually channel can detect a single transition or specified number of transitions, then cease channel activity until reinitialization ...

Page 54

... Freescale Semiconductor, Inc. 5.1.7 Period Measurement with Missing Transition Detect (PMM) Period measurement with missing transition detect allows a special-purpose 23-bit period measure- ment. It detects the occurrence of a missing transition (caused by a missing tooth on the sensed wheel), indicated by a period measurement that is greater than a programmable ratio of the previous period measurement ...

Page 55

... Freescale Semiconductor, Inc. lation parameter. From 1 to 255 period measurements can be made and summed with the previous measurement(s) before the TPU interrupts the CPU, allowing instantaneous or average frequency mea- surement, and the latest complete accumulation (over the programmed number of periods). The pulse width (high-time portion input signal can be measured ( bits) and added to a previous measurement over a programmable number of periods (1 to 255) ...

Page 56

... Freescale Semiconductor, Inc. 5.2.3 Queued Output Match (QOM) QOM can generate single or multiple output match events from a table of offsets in parameter RAM. Loop modes allow complex pulse trains to be generated once, a specified number of times, or continu- ously. The function can be triggered by a link from another TPU channel. In addition, the reference time for the sequence of matches can be obtained from another channel ...

Page 57

... Freescale Semiconductor, Inc. 5.2.9 Frequency Measurement (FQM) FQM counts the number of input pulses to a TPU channel during a user-defined window period. The function has single shot and continuous modes. No pulses are lost between sample windows in contin- uous mode. The user selects whether to detect pulses on the rising or falling edge. This function is in- tended for high speed measurement ...

Page 58

... Freescale Semiconductor, Inc. 5.4 Parameter RAM Parameter RAM occupies 256 bytes at the top of the TPU module address map. Channel parameters are organized as 128 16-bit words. However, only 100 words are actually implemented. The parameter RAM address map shows how parameter words are organized in memory. ...

Page 59

... Freescale Semiconductor, Inc. TCR1P — Timer Count Register 1 Prescaler Control TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler divides this input Channels using TCR1 have the capability to resolve down to the TPU system clock divided by 4 ...

Page 60

... Freescale Semiconductor, Inc. EMU — Emulation Control In emulation mode, the TPU executes microinstructions from MCU TPURAM exclusively. Access to the TPURAM module through the IMB by a host is blocked, and the TPURAM module is dedicated for use by the TPU. After reset, this bit can be written only once. ...

Page 61

... Freescale Semiconductor, Inc. 5.5.2 Channel Control Registers CIER — Channel Interrupt Enable Register RESET CH[15:0] — Channel Interrupt Enable/Disable 0 = Channel interrupts disabled 1 = Channel interrupts enabled CISR — Channel Interrupt Status Register RESET CH[15:0] — Channel Interrupt Status Bit 0 = Channel interrupt not asserted 1 = Channel interrupt asserted CFSR0 — ...

Page 62

... Freescale Semiconductor, Inc. HSQR0 — Host Sequence Register RESET HSQR1 — Host Sequence Register RESET CH[15:0] — Encoded Host Sequence The host sequence field selects the mode of operation for the time function selected on a given channel. The meaning of the host sequence bits depends on the time function specified. ...

Page 63

... Freescale Semiconductor, Inc. CHX[1: 5.5.3 Development Support and Test Registers These registers are used for custom microcode development or for factory test. Describing the use of the registers is beyond the scope of this technical summary. Register names and addresses are given for reference only. Please refer to the TPU Reference Manual (TPURM/AD) for more information. ...

Page 64

... Freescale Semiconductor, Inc. 6 Queued Serial Module The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). INTERFACE IMB LOGIC 6.1 Overview The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral chip- select pins provide addressability for peripheral devices ...

Page 65

... Freescale Semiconductor, Inc. 6.2 Address Map The “Access” column in the QSM address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the QSMCR. ...

Page 66

... Freescale Semiconductor, Inc. 6.3 Pin Function The following table is a summary of the functions of the QSM pins when they are not configured for gen- eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in- put or output. QSPI Pins SCI Pins 6 ...

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... Freescale Semiconductor, Inc. The system software must stop each submodule before asserting STOP to avoid complications at re- start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting STOP. The QSPI submodule should be stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set. FRZ1 — ...

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... Freescale Semiconductor, Inc. QIVR — QSM Interrupt Vector Register 15 QILR RESET: At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep- tion table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be writ- ten to QIVR during QSM initialization. ...

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... Freescale Semiconductor, Inc. Table 25 QSPAR Pin Assignments PQSPAR Field PQSPA0 PQSPA1 PQSPA2 PQSPA3 PQSPA4 PQSPA5 PQSPA6 PQSPA7 NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes SCI serial output TXD ...

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... Freescale Semiconductor, Inc. Table 26 Effect of DDRQS on QSM Pin Function QSM Pin MISO MOSI 1 SCK PCS0/SS PCS[3:1] 2 TXD RXD NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK. 2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it be- comes SCI serial output TXD ...

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... Freescale Semiconductor, Inc. 6.5 QSPI Submodule The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products. A block diagram of the QSPI is shown below. QUEUE CONTROL BLOCK ...

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... Freescale Semiconductor, Inc. Pin Names Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select Slave Select 6.5.2 QSPI Registers The programmer's model for the QSPI submodule consists of the QSM global and pin control registers, four QSPI control registers, one status register, and the 80-byte QSPI RAM. ...

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... Freescale Semiconductor, Inc. MSTR — Master/Slave Mode Select 0 = QSPI is a slave device and only responds to externally generated serial data QSPI is system master and can initiate transmission to external SPI devices. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU. WOMQ — ...

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... Freescale Semiconductor, Inc. SCK baud rate: SCK Baud Rate = System Clock/(2SPBR) SPBR = System Clock/(2SCK)(Baud Rate Desired) where SPBR equals {2, 3, 4,..., 255} Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the sys- tem clock frequency. SPCR1 — ...

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... Freescale Semiconductor, Inc. SPCR2 — QSPI Control Register SPIFIE WREN WRTO 0 RESET SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next se- rial transfer ...

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... Freescale Semiconductor, Inc. HALT — Halt 0 = Halt not enabled 1 = Halt enabled When HALT is asserted, the QSPI stops on a queue boundary defined state from which it can later be restarted. SPSR — QSPI Status Register 15 SPCR3 SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU reads this register to obtain status information and writes it to clear status flags. SPIF — ...

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... Freescale Semiconductor, Inc. D00 RR0 RR1 RR2 RECEIVE RAM RRD RRE D1E RRF WORD Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the CPU or waits for CPU intervention ...

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... Freescale Semiconductor, Inc. Command RAM is used by the QSPI when in master mode. The CPU writes one byte of control infor- mation to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer ...

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... Freescale Semiconductor, Inc. 6.6 SCI Submodule The SCI submodule is used to communicate with external devices through an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11 and M68HC05 Families. 6.6.1 SCI Pins There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI ...

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... Freescale Semiconductor, Inc. Writing a value of zero to SCBR disables the baud rate generator. The following table lists the SCBR settings for standard and maximum baud rates using 16.78-MHz and 20.97-MHz system clocks. Nominal Baud Rate Actual Rate with 16.78-MHz Clock 64* 110 110.0 300 299 ...

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... Freescale Semiconductor, Inc. PE — Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re- ceived parity bit is not correct, the SCI sets the PF error flag in SCSR. When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re- sults in either seven or eight bits of user data, depending on the condition of M bit ...

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... Freescale Semiconductor, Inc. SBK — Send Break 0 = Normal operation 1 = Break frame(s) transmitted after completion of current frame SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared. ...

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... Freescale Semiconductor, Inc. IDLE — Idle-Line Detected Flag 0 = SCI receiver did not detect an idle-line condition SCI receiver detected an idle-line condition. IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF is set when a break is received, so that a subsequent idle line can be detected. OR — ...

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... Freescale Semiconductor, Inc. 7 Standby RAM with TPU Emulation RAM The TPURAM module contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM for new timer algorithms. ...

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... Freescale Semiconductor, Inc. RASP — RAM Array Space Field 0 = TPURAM array is placed in unrestricted space 1 = TPURAM array is placed in supervisor space TRAMTST — TPURAM Test Register TRAMTST is used for factory testing of the TPURAM module. TRAMBAR — TPURAM Base Address and Status Register 15 14 ...

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... Freescale Semiconductor, Inc. 8 Summary of Changes This is a partial revision. Most of the publication remains the same, but the following changes were made to improve it. Typographical errors that do not affect content are not annotated. This document has also been reformatted for use on the web. ...

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... Freescale Semiconductor, Inc. MC68332 For More Information On This Product, MC68332TS/D Go to: www.freescale.com MOTOROLA 87 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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