MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 31

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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MC68LK332ACAG16
Manufacturer:
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1 045
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3.5.1 Chip-Select Registers
3.5.2 Pin Assignment Registers
CSPAR0 —Chip Select Pin Assignment Register 0
MC68332
MC68332TS/D
RESET:
15
0
0
Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These regis-
ters also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). Address blocks for
separate chip-select functions can overlap.
Chip-select option registers (CSORBT and CSOR[10:0]) determine timing of and conditions for asser-
tion of chip-select signals. Eight parameters, including operating mode, access size, synchronization,
and wait state insertion can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip-select circuits. A
set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
The pin assignment registers (CSPAR0 and CSPAR1) contain pairs of bits that determine the function
of chip-select pins. The pin assignment encodings used in these registers are shown below.
CSPAR0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always
reads one; writes to CSPAR0 bit 1 have no effect.
CSPAR0 Field
14
0
0
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
DATA2
13
CSPA0[6]
12
1
Freescale Semiconductor, Inc.
DATA2
11
For More Information On This Product,
CSPA0[5]
Chip Select Signal
Bit Field
Table 12 Pin Assignment Encodings
Table 13 CSPAR0 Pin Assignments
00
01
10
11
CSBOOT
10
1
CS5
CS4
CS3
CS2
CS1
CS0
Go to: www.freescale.com
DATA2
9
CSPA0[4]
Chip Select (16-Bit Port)
8
1
Chip Select (8-Bit Port)
Alternate Function
Discrete Output
DATA1
Description
7
CSPA0[3]
Alternate Signal
BGACK
6
1
FC2
FC1
FC0
BG
BR
DATA1
5
CSPA0[2]
4
1
DATA1
Discrete Output
3
CSPA0[1]
PC2
PC1
PC0
2
1
MOTOROLA
$YFFA44
1
1
CSBOOT
DATA0
0
31

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