MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 34

• Manufacturer Part Number: MC68LK332ACAG16
• Description: IC MCU 32BIT LV AMASK 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68LK332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16.78MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: QSPI, SCI, UART
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSORBT —Chip-Select Option Register Boot ROM
CSOR[10:0] —Chip-Select Option Registers
MODE — Asynchronous/Synchronous Mode
BYTE — Upper/Lower Byte Option
R/W — Read/Write
STRB — Address Strobe/Data Strobe
34
MOTOROLA
RESET:
RESET:
MODE
MODE
15
15
0
0
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an ECLK cycle is pending.
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Refer to the following table for options available.
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip select to be asserted synchronized with data strobe.
0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus con-
1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)
0 = Address strobe
1 = Data strobe
14
14
1
0
trol signals)
BYTE
BYTE
13
13
1
0
12
12
1
0
R/W
R/W
Freescale Semiconductor, Inc.
11
11
For More Information On This Product,
1
0
STRB
STRB
10
10
0
0
Go to: www.freescale.com
Byte
R/W
9
1
9
0
00
01
10
11
00
01
10
11
1
0
DSACK
DSACK
Description
Description
Lower Byte
Upper Byte
Read/Write
Both Bytes
Read Only
Write Only
Reserved
Disable
0
0
6
1
6
0
5
1
5
0
SPACE
SPACE
4
1
4
0
3
0
3
0
$YFFA4E–$YFFA76
IPL
IPL
0
0
MC68332TS/D
$YFFA4A
1
0
1
0
MC68332
AVEC
AVEC
0
0
0
0