MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1024

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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READI Module
24.9.5
Data trace windowing is achieved via the address range within the DTEA and the DTSA fields of the DTA
registers. All L-bus accesses which fall within these two address ranges, provided the address ranges are
enabled in either DTA register, are candidates to be transmitted. Data read and/or data write trace may be
enabled via the TA field of the data trace attributes registers (DTA).
24.9.6
Special L-bus cases are handled as described in
24.9.7
For queuing program trace, data trace, and ownership trace messages, READI implements a queue 32
messages deep (The queue is 16 messages deep on some versions; refer to device errata). Messages that
enter the queue are transmitted via the output auxiliary port in the order in which they are queued.
24-56
Data Trace Windowing
Special L-Bus Cases
Data Trace Queuing
L-bus Cycle Aborted
L-bus Cycle with data error
L-bus Cycle terminated due to address error
L-bus Cycle completed without error
L-bus Cycle initiated by READI (Read/Write Access)
L-bus Cycle is an instruction fetch
Data Storage Interrupt
System Reset
Data trace ranges are word aligned. Therefore, the address range fields
(DTEA and DTSA) of the DTA registers are only 23 bits wide and, as such,
should be assigned by the tool with the 23 most significant bits of the
intended 25-bit range address, i.e. the 2 LSB of the address are not used.)
The off-core MPC500 special purpose register (SPR) map cannot be
distinguished from the normal memory map accesses via the defined
address range control. If data trace ranges are set up such that the off-core
MPC500 SPR map falls within active ranges, then accesses to these off-core
MPC500 SPRs will be traced, and the messages will not be distinguishable
from accesses to normal memory map space. Off-core MPC500 SPRs
typically exist in the 8-Kbyte – 16-Kbyte lowest memory block (0x2000 -
0x3FF0). If data or peripherals are mapped to this space, load/stores to
MPC500 SPRs will be indistinguishable from data or peripheral accesses.
Special Case
Table 24-30. Special L-Bus Case Handling
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
NOTE
NOTE
24-30.
Cycle ignored
Message discarded
Cycle ignored
Cycle captured and transmitted
Cycle ignored
Cycle ignored
Cycle ignored
Cycle ignored
Action
Freescale Semiconductor

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