MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1169

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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D.8
The COMM function generates phase commutation signals for a variety of brushless motors, including
three-phase brushless direct current motors. It derives the commutation state directly from the position
decoded in FQD, eliminating the need for hall effect sensors.
The state sequence is implemented as a user-configurable state machine, providing a flexible approach
with other general applications. A RCPU offset parameter is provided to allow the RCPU to advance or
retard all swtiching angles on the fly. This feature is useful for torque maintenance at high speeds. See
Freescale TPU Progamming Note Multiphase Motor Commutation TPU Function (COMM),
(TPUPN09/D).
Figure D-10
Freescale Semiconductor
Multiphase Motor Commutation (COMM)
and
Figure D-10
show all of the host interface areas for the COMM function.
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure D-9. NITC Parameters
CONTROL BITS
See
PRAM Address Offset Map.
Table 19-24
for the
TPU3 ROM Functions
D-17

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