MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1234

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Electrical Characteristics
If the PORESET or HRESET signal is not asserted before this condition, there is a possibility of disturbing
the programmed state of the flash. In addition, the state of the pads are indeterminant until PORESET or
HRESET propagates through the device to initialize all circuitry.
F.9.2
PORESET or HRESET must be asserted during power-down prior to any supply dropping out of specified
operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input. To assure that
the assertion of PORESET does not potentially cause stores to keep-alive RAM to be corrupted (store
single or store multiple) or non-coherent (store multiple), either of the following solutions is
recommended:
The amount of delay that should be added to PORESET assertion is dependent upon the frequency of
operation and the maximum number of store multiples executed that are required to be coherent. If store
multiples of more than 28 registers are needed and if the frequency of operation is lower that 56 MHz, the
delay added to PORESET assertion will need to be greater than 0.5 µs. In addition, if KAPWR features
are being used, PORESET should not be driven low while the V
F.10
Figure F-9
in
F-18
Figure F-10
•
•
Assert HRESET at least 0.5 µs prior to when PORESET is asserted.
Assert IRQ0 (non-maskable interrupt) at least 0.5 µs prior to when PORESET is asserted. The
service routine for IRQ0 should not perform any writes to keep-alive RAM.
AC Timing
displays generic examples of MPC561/MPC563 timing. Specific timing diagrams are shown
Keep-Alive RAM
through
Figure
F-36.
MPC561/MPC563 Reference Manual, Rev. 1.2
DDH
and V
DDL
supplies are off.
Freescale Semiconductor