MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1331

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Note: (V
Freescale Semiconductor
1
2
3
4
5
DD
27d
28a
28
29
30
The timing for BR output is relevant when the deviceMPC561/MPC563 is selected to work with external bus
arbiter. The timing for BG output is relevant when the MPC561/MPC563 is selected to work with internal bus
arbiter.
The setup times required for TA, TEA, and BI are relevant only when they are supplied by the external device
(and not the memory controller).
The maximum value of spec 8 for DATA[0:31] pins must be extended by 1.1 ns if the pins have been precharged
to greater than V
VDATAPC. This is currently specified at 3.1 V. The 1.1 ns addition to spec 8 reflects the expected timing
degradation for 3.1 V.
The device may be used without limitation in conjuction with 2.6 V external memories. Pre-discharge function
is not available for 66-MHz operation.
The timing 27 refers to CS when ACS = ‘00’ and to WE[0:3]/BE[0:3] when CSNT = ‘0’.
= 2.6 V ± 0.1 V, V
CLKOUT
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’, ACS = 10,ACS = =’11’,
EBDF = 1
Edge. (Slave mode Setup Time)
Slave Mode D[0:31] valid to CLKOUT Rising Edge
TS valid to CLKOUT Rising Edge (Setup Time)
CLKOUT Rising Edge to TS Valid (Hold Time).
ADDR[8:31], TSIZ[0:1], RD/WR, BURST, valid to CLKOUT Rising
The D[0:31] input timings 17 and 18 refer to the rising edge of the CLKOUT
in which the TA input signal is asserted.
DDL
DDH
. This is the case if an external slave device on the bus is running at the max. value of
= 5.0 V ± 0.25 V, T
Table G-10. Bus Operation Timing (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Characteristic
5
Figure G-10. CLKOUT Pin Timing
4
A
= T
L
NOTE
to T
H
, 50 pF load unless noted otherwise)
3
1
2
14.65
Min
3.5
3.7
3.6
2
66-MHz Electrical Characteristics
66 MHz
Max
Uni
ns
ns
ns
ns
ns
t
G-25

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