MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 141

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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B_AN[48:51]/
B_AN[52:54]/
B_AN[55:59]/
Signal List
B_PQB[4:7]
B_PQA[0:2]
B_PQA[3:7]
VFLASH
B_MA[0:2]/
B0EPEE
A_CNRX0
B_CNRX0
A_CNTX0
B_CNTX0
B_PQB3
VDDF
B_AN3 /
B_ANz /
VSSF
EPEE
18
18
18
18
18
1
Voltage
2.6 V
2.6 V
2.6 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
0 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Controlled
Slew Rate
Option?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
50 ; 50
50 ; 50
50 ; 50
50 ; 50
50 ; 50
50 ; 50
Drive
Load
(pF)
TouCAN_A / TouCAN_B
NA
NA
NA
NA
NA
NA
NA
NA
UC3F Power Supplies
2
17
17
5
5
5
5
UC3F Flash
PU5 when driver
not enabled or
until
PULL_DIS2 is
set
PU5 when driver
not enabled or
until
PULL_DIS2 is
set
PU5 when driver
not enabled or
until
PULL_DIS2 is
set
PU5 when driver
not enabled or
until
PULL_DIS2 is
set
PU5 until
PULL_DIS3 is
set
PU5 until
PULL_DIS3 is
set
PU5 until
PULL_DIS3 is
set
PU5 until
PULL_DIS3 is
set
PU2.6
PU2.6
Reset State
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
s
B_AN3
B_AN[48:51]
B_AN[52:54]
B_AN[55:59]
A_CNTX0
B_CNTX0
A_CNRX0
B_CNRX0
EPEE
B0EPEE
VFLASH
VDDF
VSSF
Function After HRESET,
PORESET/TRST
Signal Descriptions
2-43

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