MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 149

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The following sections describe these execution units in greater detail.
3.4.1
The BPU, located within the instruction sequencer, performs condition register look-ahead operations on
conditional branches. The BPU looks through the instruction queue for a conditional branch instruction
and attempts to resolve it early, achieving the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore,
when it encounters an unresolved conditional branch instruction, the processor pre-fetches instructions
from the predicted target stream until the conditional branch is resolved.
The BPU uses a calculation feature to compute branch target addresses with three special-purpose,
user-accessible registers: the link register (LR), the count register (CTR), and the condition register (CR).
The BPU calculates the return pointer for a subroutine, then calls and saves it into the LR. The LR also
contains the branch target address for the branch conditional to link register (bclrx) instruction. The CTR
contains the branch target address for the branch conditional to count register (bcctrx) instruction. The
contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers
rather than general-purpose or floating-point registers, execution of branch instructions is independent
from execution of integer instructions. The CR bits indicate conditions that may result from the execution
of relevant instructions.
3.4.2
The IU executes all integer processor instructions (except the integer storage access instructions)
implemented by the load/store unit. The IU contains the following subunits:
The IU also includes the integer exception register (XER) and the general-purpose register file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–BFU unit can
execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles to execute.
IMUL–IDIV is pipelined for multiply instructions, so that consecutive multiply instructions can be issued
Freescale Semiconductor
The IMUL–IDIV unit, which implements the integer multiply and divide instructions
The Arithmetic Logic Unit (ALU)–BFU unit, which implements all integer logic, add, subtract,
and bit-field instructions
Floating-point unit (FPU)
Branch Processing Unit (BPU)
Integer Unit (IU)
Integer unit (IU)
Unit
Table 3-1. RCPU Execution Units (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Includes implementation of all integer instructions except load/store instructions.
This module includes the GPRs (including GPR history and scoreboard) and the
following subunits: the IMUL-IDIV, which includes the implementation of the
integer multiply and divide instructions and the ALU-BFU, which includes
implementation of all integer logic, add and subtract instructions, and bit field
instructions.
Includes the FPRs (including FPR history and scoreboard) and the
implementation of all floating-point instructions except load/store floating-point
instructions.
Description
Central Processing Unit
3-5

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