MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 158

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Central Processing Unit
A listing of FPSCR bit settings is shown in
3-14
Bits
Reset
Reset
10
11
0
1
2
3
4
5
6
7
8
9
Field FX FEX VX
Field
MSB
VXSNAN
16
0
VXZDZ
VXIMZ
Name
VXIDI
VXISI
FEX
OX
UX
FX
VX
ZX
XX
FPRF[1:4]
17
1
Figure 3-6. Floating-Point Status and Control Register (FPSCR)
18
Floating-point exception summary. Every floating-point instruction implicitly
sets FPSCR[FX] if that instruction causes any of the floating-point exception
bits in the FPSCR to change from 0 to 1. The mcrfs instruction implicitly clears
FPSCR[FX] if the FPSCR field containing FPSCR[FX] has been copied. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX]
explicitly.
Floating-point enabled exception summary. This bit signals the occurrence of
any of the enabled exception conditions. It is the logical OR of all the
floating-point exception bits masked with their respective enable bits. The
mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR
described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1
instructions cannot set or clear FPSCR[FEX] explicitly.
Floating-point invalid operation exception summary. This bit signals the
occurrence of any invalid operation exception. It is the logical OR of all of the
invalid operation exceptions. The mcrfs instruction implicitly clears
FPSCR[VX] if the result of the logical OR described above becomes zero. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX]
explicitly.
Floating-point overflow exception.
Floating-point underflow exception.
Floating-point zero divide exception.
Floating-point inexact exception.
Floating-point invalid operation exception for SNaN.
Floating-point invalid operation exception for ∞ - ∞.
Floating-point invalid operation exception for ∞/∞.
Floating-point invalid operation exception for 0/0.
Floating-point invalid operation exception for ∞ x 0.
2
OX
19
3
UX
20
0
4
MPC561/MPC563 Reference Manual, Rev. 1.2
SOFT
Table 3-5. FPSCR Bit Descriptions
ZX
VX
21
5
SQRT
XX
VX
22
6
Table
VXCVI
VXSN
AN
23
3-5.
7
Unchanged
Unchanged
VXISI VXIDI VXZDZ VXIMZ VXVC FR
VE
24
8
Description
OE
25
9
UE
10
26
ZE
11
27
XE
12
28
Freescale Semiconductor
NI
13
29
Not sticky
Not sticky
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
Sticky bit
14
30
FI FPRF0
RN
LSB
15
31

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