MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 165

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Bits
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
FE0
FE1
ILE
ME
EE
PR
SE
BE
FP
IP
IR
Table 3-11. Machine State Register Bit Descriptions (continued)
Reserved
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception. Little-endian mode is not
supported on the MPC561/MPC563. This bit should be cleared to 0 at all times.
0 The processor runs in big-endian mode during exception processing.
1 The processor runs in little-endian mode during exception processing.
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts (EE = 0) in the RCPU before clearing or masking any
interrupt source from the USIU or external pins. For external interrupts, it is recommended that
the edge-triggered interrupt scheme be used. See
Controller.”
0 The processor delays recognition of external interrupts and decrementer exception
1 The processor is enabled to take an external interrupt or the decrementer exception.
Privilege level.
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
Floating-point available.
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
1 The processor can execute floating-point instructions, and can take floating-point enabled
Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
Floating-point exception mode 0 (See
Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
Floating-point exception mode 1 (See
Reserved
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
Instruction relocation.
0 Instruction address translation is off; the BBC IMPU does not check for address permission
1 Instruction address translation is on; the BBC IMPU checks for address permission
conditions.
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
exception type program exceptions.
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception.
attributes.
attributes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
Table
Description
3-12.)
3-12).
Section 6.1.4, “Enhanced Interrupt
Central Processing Unit
3-21

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