MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 167

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

3.9.3
After an alignment exception, the DAR, SPR 19, is set to the effective address of a load or store element.
3.9.4
Refer to
3.9.5
Refer to
3.9.6
The machine status save/restore register 0 (SRR0), SPR 26, identifies where instruction execution should
resume when an rfi instruction is executed following an exception. It also holds the effective address of
the instruction that follows the system call (sc) instruction.
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have
completed execution and no subsequent instruction has begun execution. The instruction addressed by
SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the
instruction causing the exception or the instruction immediately following. The instruction addressed can
be determined from the exception type and status bits.
3.9.7
The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and
restores the machine status when an rfi instruction is executed.
Freescale Semiconductor
Reset
Reset
Field
Addr
Field
Addr
Section 6.1.7, “Time Base
Section 6.1.6, “Decrementer
MSB
Data Address Register (DAR)
Time Base Facility (TB) — OEA
Decrementer Register (DEC)
Machine Status Save/Restore Register 0 (SRR0)
Machine Status Save/Restore Register 1 (SRR1)
MSB
0
0
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
2
3
Figure 3-14. Machine Status Save/Restore Register 0 (SRR0)
4
5
6
7
Figure 3-13. Data Address Register (DAR)
MPC561/MPC563 Reference Manual, Rev. 1.2
8
(TB),” for information.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(DEC),” for information.
Data Address
Unchanged
Undefined
SPR 26
SPR 19
SRR0
Central Processing Unit
LSB
31
LSB
31
3-23