MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 169

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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3.9.9
The PVR is a 32-bit, read-only register that identifies the version and revision level of the processor. The
contents of the PVR can be copied to a GPR by the mfspr instruction. Read access to the PVR is available
in supervisor mode only; write access is not provided.
3.9.10
The MPC561/MPC563 includes several implementation-specific SPRs that are not defined by the
PowerPC ISA architecture. These registers, listed in
supervisor-level instructions only.
3.9.10.1
The RCPU includes three implementation-specific SPRs that facilitate the software manipulation of the
MSR[RI] and MSR[EE] bits: External Interrupt Enable (EIE), External Interrupt Disable (EID), and
Non-recoverable Interrupt (NRI). Issuing the mtspr instruction with one of these registers as an operand
causes the RI and EE bits to be set or cleared as shown in
A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software
emulation exception.
Freescale Semiconductor
16:31
Bits
0:15
Reset
Field
Addr
Processor Version Register (PVR)
Implementation-Specific SPRs
MSB
EIE, EID, and NRI Special-Purpose Registers
0
REVISION
VERSION
Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0000_0000_0000_0010
Table 3-14. Processor Version Register Bit Descriptions
A 16-bit number that identifies the version of the PowerPC ISA processor. The RCPU value
is 0x0002.
A 16-bit number that distinguishes between various releases of a particular version. The
RCPU value is 0x0020.
VERSION
Figure 3-17. Processor Version Register (PVR)
SPR Number
(Decimal)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-15. EIE, EID, AND NRI Registers
80
81
82
Mnemonic
EID
NRI
EIE
Table 3-2
SPR 287
MSR[EE]
Table
Description
1
0
0
and
3-15.
Table
MSR[RI]
0000_0000_0010_0000
1
1
0
3-3, can be accessed by
REVISION
Central Processing Unit
LSB
31
3-25

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