MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 18

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

14.4.4.2
14.4.4.3
14.4.4.3.1
14.4.4.3.2
14.4.4.3.3
14.4.4.3.4
14.4.4.4
14.4.4.4.1
14.4.4.4.2
14.4.4.4.3
14.4.4.4.4
14.4.5
14.4.6
14.4.7
14.4.7.1
14.4.7.2
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1
14.6.4
14.6.5
14.6.5.1
14.6.5.2
14.6.5.3
14.6.5.4
15.1
15.2
15.2.1
15.3
15.4
15.4.1
15.4.2
Freescale Semiconductor
Paragraph
Number
Trigger and Queue Interaction Examples ................................................................... 14-53
QADC64E Integration Requirements ......................................................................... 14-65
Block Diagram .............................................................................................................. 15-1
Key Features ................................................................................................................. 15-2
Memory Maps ............................................................................................................... 15-4
QSMCM Global Registers ............................................................................................ 15-6
QADC64E Clock (QCLK) Generation ................................................................... 14-48
Periodic/Interval Timer ........................................................................................... 14-50
Configuration and Control Using the IMB3 Interface ............................................ 14-51
Queue Priority Schemes .......................................................................................... 14-53
Conversion Timing Schemes .................................................................................. 14-62
Port Digital Input/Output Signals ........................................................................... 14-65
External Trigger Input Signals ................................................................................ 14-66
Analog Power Signals ............................................................................................. 14-66
Analog Reference Signals ....................................................................................... 14-69
Analog Input Signals .............................................................................................. 14-70
MPC561/MPC563 QSMCM Details ........................................................................ 15-3
Low-Power Stop Operation ...................................................................................... 15-6
Freeze Operation ....................................................................................................... 15-6
Reserved Mode ................................................................................................... 14-42
Single-Scan Modes ............................................................................................. 14-43
Continuous-Scan Modes ..................................................................................... 14-45
QADC64E Bus Interface Unit ............................................................................ 14-51
QADC64E Bus Accessing .................................................................................. 14-51
Analog Supply Filtering and Grounding ............................................................ 14-67
Analog Input Considerations .............................................................................. 14-71
Settling Time for the External Circuit ................................................................ 14-73
Error Resulting from Leakage ............................................................................ 14-73
Accommodating Positive/Negative Stress Conditions ....................................... 14-74
Software Initiated Single-Scan Mode ............................................................. 14-43
External Trigger Single-Scan Mode ............................................................... 14-44
External Gated Single-Scan Mode ................................................................. 14-44
Periodic/Interval Timer Single-Scan Mode .................................................... 14-45
Software Initiated Continuous-Scan Mode ..................................................... 14-46
External Trigger Continuous-Scan Mode ....................................................... 14-47
External Gated Continuous-Scan Mode ......................................................... 14-47
Periodic/Interval Timer Continuous-Scan Mode ............................................ 14-48
Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 15
Title
Number
Page
xviii