MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 192

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Central Processing Unit
when a machine check exception is taken, instruction execution resumes at offset 0x0200 from the base
address indicated by MSR[IP].
3.15.4.3
A data storage exception is never generated by the RCPU. The software may branch to this location as a
result of implementation-specific data storage protection error exception.
3.15.4.4
An instruction storage interrupt is never generated by them RCPU. The software may branch to this
location as a result of an implementation-specific instruction storage protection error exception.
3.15.4.5
The external interrupt exception is taken on assertion of the internal IRQ line to the RCPU, that is driven
by on-chip interrupt controller. The interrupt may be caused by the assertion of an external IRQ signal, by
a USIU timer, or by an internal chip peripheral. Refer to
for more information on the interrupt controller.
3-48
1
2
3
If the exception occurs due to a data error caused by a Load/Store instruction and the processor in Decompression
On mode, the SRR0 register will contain the address of the Load/Store instruction in compressed format. If the
exception occurs due to an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in MSR is
loaded from this bit when an RFI is executed.
DSISR and DAR registers are only updated when the machine check exception is caused by a data access violation.
Machine State Register (MSR)
Data Address Register (DAR)
Data/Storage Interrupt Status
Register (DSISR)
Register Name
Data Storage Exception (0x0300)
Instruction Storage Exception (0x0400)
External Interrupt (0x0500)
Table 3-25. Register Settings following a Machine Check Exception (continued)
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
Other
15:16
18:21
22:31
Bits
0:14
ME
LE
17
All
IP
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
D-form
Set to bits [21:24] of the instruction if X-form and to bits [1:4] if
D-form
Set to bits [6:15] of the instruction
Set to the effective address of the data access that caused the
interrupt
No change
Cleared to 0
Set to bits [29:30] of the instruction if X-form and to 0b00 if
Set to bit 25 of the instruction if X-form and to Bit 5 if D-form
Section 6.1.4, “Enhanced Interrupt
Description
Freescale Semiconductor
Controller,”

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