MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 193

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

The interrupt may be delayed by other higher priority exceptions or if the MSR[EE] bit is cleared when
the exception occurs. MSR[EE] is automatically cleared by hardware to disable external interrupts when
any exception is taken.
Upon detecting an external interrupt, the processor assigns it to the instruction at the head of the history
buffer (after retiring all instructions that are ready to retire).
The enhanced interrupt controller mode is available for interrupt-driven applications on
MPC561/MPC563. It allows the single external interrupt exception vector 0x500 to be split into up to 48
different vectors corresponding to 48 interrupt sources to speed up interrupt processing. It also supports a
low priority source masking feature in hardware to handle nested interrupts more easily. See
“Enhanced Interrupt
The register settings for the external interrupt exception are shown in
When an external interrupt is taken, instruction execution resumes at offset 0x00500 from the physical
base address indicated by MSR[IP].
3.15.4.6
The following conditions cause an alignment exception:
Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to determine the
source of the exception.
The register settings for alignment exceptions are shown in
Freescale Semiconductor
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
address in compressed format.
Machine State Register (MSR)
The operand of a floating-point load or store instruction is not word-aligned.
The operand of a load or store multiple instruction is not word-aligned.
The operand of lwarx or stwcx. is not word-aligned.
Alignment Exception (0x00600)
Register
Controller,” and
Table 3-26. Register Settings following External Interrupt
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPE
[16:31]
[0:15]
Other
Bits
ME
LE
All
IP
N
Chapter 4, “Burst Buffer Controller 2
Set to the effective address of the instruction that the processor would
have attempted to execute next if no interrupt conditions were present.
Cleared to 0
Loaded from bits [16:31] of MSR. In the current implementation, bit 30
of the SRR1 is never cleared, except by loading a zero value from
MSR[RI]
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
No change
No change
Cleared to 0
Table
Setting Description
3-27.
Table
Module.”
3-26.
Central Processing Unit
Section 6.1.4,
3-49