MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 269
MPC562MZP56
Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC562MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
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Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
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6.2.2.1.3
The external master control register selects the external master modes and determines the internal bus
attributes for external-to-internal accesses.
Freescale Semiconductor
16:19
21:22
24:27
28:30
Bits
8:15
0:7
20
23
31
MASKNUM
PARTNUM
External Master Control Register (EMCR)
Name
FLEN
ISB
—
—
—
—
—
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC561 has
an ID of 0x35. The MPC563 has an ID of 0x36.
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
Reserved
Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot
is performed from external memory. This bit can be set at reset by the reset configuration
word.
0 On-chip Flash memory is disabled, and all internal cycles to the allocated Flash address
space are mapped to external memory
1 On-chip Flash memory is enabled
Reserved
Reserved. This bit should be programmed to 0 at all times.
Reserved
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 0x0000 0000
001 0x0040 0000
010 0x0080 0000
011 0x00C0 0000
100 0x0100 0000
101 0x0140 0000
110 0x0180 0000
111 0x01C0 0000
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-12. IMMR Bit Descriptions
Description
System Configuration and Protection
6-29
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