MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 277

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

SRESET
SRESET
6.2.2.2.9
SISR2, SISR3 are 32-bit read/write registers. Each bit in the register corresponds to an interrupt request.
A bit is set if:
Once a bit is set, all requests with lower or equal priority become masked (i.e. they will not generate any
interrupt request to the RCPU) until the bit is cleared. A bit is cleared by writing a ‘1’ to it. Writing zero
has no effect.
6.2.2.3
6.2.2.3.1
The system protection control register (SYPCR) controls the system monitors, the software watchdog
period, and the bus monitor timing. This register can be read at any time, but can be written only once after
system reset.
Freescale Semiconductor
SRESET
SRESET
Field IRQ0
Field IMB
Addr
•
•
Field IMB
Field
Addr
There is a pending interrupt request (SIPEND2/3), that is not masked by (SIMASK2/3), and
The BBC/IMPU acknowledges interrupt request and latches SIVEC value.
IRQ10
MSB
IRQ20
16
0
MSB
16
0
System Protection Registers
IRQ11
LVL0
Interrupt In-Service Registers (SISR2 and SISR3)
System Protection Control Register (SYPCR)
IMB
17
IRQ21
1
IMB
17
1
IRQ0
IRQ3 LVL4
IMB
18
2
IRQ22
IMB
18
2
IRQ1
IMB
Figure 6-24. Interrupt In-Service Register 2 (SISR2)
Figure 6-25. Interrupt In-Service Register 3 (SISR3)
19
3
IRQ23
IMB
19
3
IRQ12
IRQ2
IMB
IMB
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
IRQ
20
6
4
IRQ13
IRQ3
IMB
IMB
21
LVL
5
21
5
6
IRQ14
IRQ24
IRQ1
IMB
IMB
22
6
0000_0000_0000_0000
0000_0000_0000_0000
22
0000_0000_0000_0000
0000_0000_0000_0000
6
IRQ15
IRQ25
LVL1
IMB
0x2F C050
0x2F C054
IMB
23
7
23
7
—
IRQ4
IRQ4 LVL4
IRQ26
IMB
IMB
24
8
24
8
IRQ5
IMB
IRQ27
25
9
IMB
25
9
IRQ16
IRQ6
IMB
IMB
IRQ
10
26
10
26
7
LVL
IRQ17
System Configuration and Protection
IRQ7
11
27
7
IMB
IMB
11
27
IRQ28
IMB
12
28
IRQ18
IRQ2
IMB
12
28
IRQ29
IMB
13
29
IRQ19
LVL2
IMB
13
29
IRQ30
IMB
14
30
IRQ8
IRQ5 LVL5
IMB
14
30
IRQ31
IMB
LSB
15
31
IRQ9
IMB
6-37
LSB
15
31